Despite the high configurability of IPs and hardware generators, code modifications are still required to introduce aspect-oriented instrumentation to satisfy emerging aspectual design requirements such as on-chip debug and functional safety. These code modifications escalate development, verification efforts, and deteriorate code reuse. This paper proposes a highly efficient transformative hardware design methodology that leverages graph-grammar-based model transformations. Following the proposed methodology, main design functionalities and aspectual instrumentation are separately developed, automatically integrated, and verified. To demonstrate the applicability, industrial SoCs were transformed to support on-chip debug. Compared to the manual RTL coding, the proposed transformative methodology needed less than 32x Lines of Code (LoC) to develop and integrate the aspectual instrumentation. In particular, our approach enables high code reusability, as the implementation of the transformation script is a one-time effort, and can be applied to all evaluated SoCs. This high LoC gain and code reuse promote the overall productivity of digital design.

Despite the high configurability of IPs and hardware generators, code modifications are still required to introduce aspect-oriented instrumentation to satisfy emerging design requirements such as on-chip debug and functional safety. These code modifications lead to escalated development, verification efforts and deteriorate the code reuse. This paper proposes a highly efficient aspect-oriented design automation approach that leverages graph-grammar-based model transformations. With the proposed approach, main design functionalities and aspect-oriented instrumentation are separately developed, automatically integrated and verified. To demonstrate the applicability, industrial SoCs were transformed to support on-chip debug. Experimental results confirm the efficiency of the approach. Further, reduced code is needed with the proposed automation approach, which also replaces the error-prone manual RTL coding. Finally, the transformation scripts are applicable to different SoCs, which promotes the overall code reuse.

As various domain knowledge is prerequired, the embedded systems development is difficult. In the development process, multiple programming languages are used to develop different aspects such as hardware, firmware and formal verification. The semantic gap and inconsistent syntax among these languages escalate further the design efforts. We propose to generate Python-embedded Self-Verifying Domain-Specific Languages (DSLs) from metamodels. Domainspecific semantics are captured in metamodels. With additional configurations, domain-specific functionalities are included in DSLs. Further, tests are generated to assure the DSL quality. To demonstrate the applicability, the proposed approach is applied on an embedded system automation framework that generates hardware, firmware and formal properties for verification. An SoC was generated and verified with the automation framework. Minimal efforts were observed to achieve high code coverage for DSLs. Furthermore, our approach scales well with increasing domain complexity, i.e., the generation took less than 10 seconds for the most complex DSL (129.9k Lines of Code).

Safety-critical designs used in automotive applications need to ensure reliable operations even under hostile operating conditions. As these designs grow in size and complexity, they are facing an increased risk of failure. Consequently, the methods applied to validate the reliability of designs require increasingly more compute resources (e.g., fault simulation time) and manual efforts. Rigorous and highly automated safety analysis methods are needed to cope with this rising complexity. In this paper, we propose a model-based safety analysis flow to enable fault injection at different abstraction levels of a design. The fault simulation is performed at register transfer level (RTL) of a design, in which parts of the design targeted for fault simulation are represented with gate-level granularity. This mixed representation of a design provides a significant rise in fault simulation performance while maintaining the same accuracy as a gate-level fault simulation. To demonstrate the applicability of the proposed approach, various RISC- V based CPU subsystems that are part of automotive SoCs are considered for fault simulation. The experimental results show an increase of 3.5x - 8.4x in the fault simulation performance with substantially less manual effort as all the design activities are automated utilizing a model-driven RTL generation flow.

The AI-hype started a few years ago, with advances in object recognition. Soon the EDA research community made proposals on applying AI in EDA and all major players announced new AI-based tools at DAC 2018. Unfortunately, few new AI-based EDA-tools made it to productive use today. This talk analyses general challenges of AI in EDA, outlines promising use cases, and motivates more AI research in EDA: More HI (=Human Intelligence) is needed to make AI successful in EDA.

Fault tolerance enables the system to avoid threats (fail-safe) or continue with its safe operational functionality even in the presence of random faults. This ability comes at the cost of additional development efforts and the silicon overhead required to harden the critical elements. The hardening process adds the safety mechanisms around the critical elements of the system such as registers and memory. In this paper, we present an approach to develop fault-tolerant systems by automating the hardening process, hence increasing design productivity. The process also helps to reduce overhead by very focused and critically guided insertion of safety mechanisms. By comparing our approach to a commercial generic safety IP, reduced development efforts, simpler integration and less overhead are observed. To demonstrate the applicability, an arbitrary number of registers in an SoC were hardened automatically. The experimental results show that our approach scales with a growing number of safety requirements.

The HW/SW interface is a common and crucial component in System-on-Chips, enabling the interaction between software and hardware. Generating architecture and firmware code of the interface from extended IP-XACT, SystemRDL, or proprietary formalism is an established technology. This paper describes a new area and performance optimization step in the HW/SW interface generation process that reduces the silicon area and hardware access time through firmware. Three improvements of the underlying formalism are applied to achieve the optimization: First, a decoupling of bit fields from registers, which allows the rearrangement of the memory layout easily. Second, the specification of hardware accesses, which constraints the bit field arrangement. Third, different implementations of bit field accesses, such as memory-mapped or via CPU special registers. The used generation framework follows the approach of model-driven architecture, which includes optimization. Initially, abstract models specify the requirements of the IP or the HW/SW interface. Transformations turn these models into platformindependent models of hardware and firmware. These models are further transformed into implementation-specific models of a target language, such as hardware description languages or C. The proposed optimization has been successfully applied to peripheral variants of a CPU subsystem used in an industrial demonstrator. An area reduction of 19% and a performance gain of 11% has been achieved by optimizing the interfaces.

This paper presents an automated process for end-to-end embedded system design following OMG's model driven architecture (MDA) vision. It tackles a major challenge in automation: bridging the large semantic gap between the specification and the target code. The shown MDA adaption proposes an uniform and systematic way by splitting the translation process into multiple layers and introducing design platform independent and implementation independent views.In our adaption of MDA, we start with a formalized specification and we end with code (view) generation. The code is then compiled (software) or synthesized (hardware) and finally assembled to the embedded system design. We split the translation process in Model-of-Thing (MoT), Model-of-Design (MoD) and Model-of-View (MoV) layers. MoTs represent the formalized specification, MoDs contain the implementation architecture in a view independent way, and MoVs are implementation dependent and view dependent, i.e., specific details in target language.MoT is translated to MoD, MoD is translated to MoV and MoV is finally used to generate views. The translation between the Models is based on templates, that reflect design and coding blueprints. The final step of the view generation is itself part of generation. The Model MoV and the unparse method are generated from a view language description.The approach has been successfully adapted for generating digital hardware (RTL), properties for verification (SVA), and snippets of firmware that have been successfully synthesized to an FPGA.

Design productivity remains a big problem in current embedded system development. Domain-Specific Languages (DSLs) are a promising measure to accelerate the development cycle. However, the inconsistent syntax in various DSLs, during system development and manual DSL development negatively impact any gained productivity. In this paper, we propose a metamodel-based framework for the generation of Python-embedded DSLs. A target metamodel abstracts models by defining elementary building blocks. With an additional configuration, our framework generates an expressive DSL which automates model construction and enables dataflow programming. By applying the proposed framework on different target meta-models, a “One Language Ecosystem” is formed with the generated DSLs describing RTL, firmware and formal properties. As a proof of concept, a System on a Chip (SoC) consisting of RTL code and a firmware stack is generated, and formal properties are automated to verify the hardware components. To develop the RTL DSL, a time reduction by a factor-of-six is observed by using this generative approach. Furthermore, by comparing the DSL description to the generated target code, a code reduction by a factor-of-eight is given.

This paper presents a practical methodology for applying formal verification on industrial designs. The methodology is developed considering the quality, efficiency and productivity required in an industrial verification setup. The flow proposes a systematic approach addressing various aspects of the formal verification. First, the design implementation (RTL) is analyzed for its formal friendliness based on several predefined criteria. Next, a property automation flow is adapted for an efficient property development. Later, a series of verification tasks, grouped into formal test plan and formal execution plan are carried out to reach the formal sign-off stage. To demonstrate the applicability and effectiveness of the methodology, the proposed flow has been successfully applied on several industrial designs. In this paper, we consider the formal verification of Error Correction Codes, generally implemented in program and data flash memory interfaces to benchmark the proposed flow. Automatic property generation flow is used to generate an optimal property set with varying abstraction levels. The property proof runtimes are drastically reduced and better coverage compared to the previous hand-written properties has been achieved. New RTL bugs and specification errors have been found that were previously missed during the simulation.

To cope with the strict reliability requirements of safety-critical ADAS applications, the upcoming TSN standard introduces mechanisms that enable transmission redundancy at any switch or end node. However, it is up to the designer to decide at which points and for which messages to activate transmission redundancy. This significantly increases the design space and requires to trade-off reliability with other routing-related design objectives like network load, transmission timing, or the monetary cost of the hardware. As a remedy, this paper a) presents two different exact approaches to generate feasible redundant message routings and b) proposes an extension of the state-of-the-art approach for the multi-objective routing optimization, enabling the optimizer to directly adjust system features that are relevant for the design objectives. A case study with an application from the automotive domain compares the optimization capabilities of the presented approaches for the routing generation and demonstrates the significant gain in optimization power that is achieved with the proposed optimization extension.