A type of tunable femtosecond soliton logic gate based on fiber Raman Self-Frequency Shift (SFS) is studied in this paper. The Raman SFSs of femtosecond solitons governed by the Newton's cradle mechanism in logic gate are analyzed with an Improved Split-Step Fast Fourier Transform (ISSFFT) algorithm. The impact factors of the solitonic pulse frequency shift and temporal time shift, which are included the Third-Order Dispersion (TOD) effect, are investigated. The existing theoretical equation of SFS is modified into a new expression for this type of soliton logic gate. A lower switching power and the small size of the soliton logic gate device is designed to realize the logic functions of AND, NOT, and XOR. The results demonstrate that the logic gate based on SFS is belonged to the asynchronous system and can be achieved with Milli-Watt switching power and good extinction ratio. ISSFFT is effective and accurately to analyze higher-order dispersive and nonlinear effects in the logic gates.

By summarizing some classical active contour models from the view of level set representation, a simple energy function expression with the Gaussian kernel of fractional order is proposed, and then a novel region-based geometric active contour model is established. In this proposed model, the energy function with value of [−1, 1] is built, the local mean and global mean of the inside and outside of the evolution curve are employed, and the segmentation results are obtained by controlling the expansion and contraction of the evolution curve. The model is simple and easy to implement; it can also protect weak edges because of considering more statistical information. Experimental results on synthetic and natural images show that the proposed model is much more effective in dealing with the images with weak or blurred edges, and it takes less time.

A wavelength-multiplexing phase-sensitive surface plasmon resonance (SPR) imaging sensor offering wide dynamic detection range and microarray capability is reported. Phase detection is accomplished by performing self-interference between the s- and p- polarizations within the signal beam. A liquid crystal tunable filter is used to sequentially select the SPR excitation wavelength from a white light source. This wavelength-multiplexing approach enables fast detection of the sensor's SPR phase response over a wide range of wavelengths, thereby covering literally any regions of interest within the SPR dip and thus maintaining the highest sensitivity point at all times. The phase-sensitive approach is particularly important for imaging SPR sensing applications because of its less stringent requirements for intensity signal-to-noise ratio, which also means the possibility of using uncooled modest resolution analog-to-digital conversion imaging devices. Experimental results demonstrate a resolution of 2.7×10(-7) RIU with a dynamic range of 0.0138 RIU.

This paper presents an analytical method of low power standard cell library design for high efficient energy saving system. Based on the optimization of P/N width ratio, this method reduces both transistor size and power consumption in order to improve the energy efficiency of basic building blocks in the library. The library was realized in a 180 nm standard CMOS process and the maximum operating frequency is 50 MHz. In order to verify its performance, the library was applied to build an 8-bit adder using digital ASIC component development flow. The results show that a reduction of 43% power consumption was achieved. The library and the corresponding design flow developed in this paper meet the requirements of high efficient energy saving system design.

CMOS active pixel sensors have been proved to be promising technique for next generation vertex detector. As a good spatial resolution is required by the vertex detector, a column-based fully offset compensated 5-bit Analog-to-Digital Converter has been designed. The ADC is based on successive approximation architecture. In order to avoid use a large binary capacitor array, multiple references are used. Charge redistribution is achieved by applying different reference voltages. All the three dynamic reference voltages are independent and adjustable externally, which gives access to compensate the undesirable errors bit by bit. An external adjustable threshold value is used for triggering the conversion. An auto-zeroed sample and hold block has been designed to work in parallel with the ADC so that pipeline delay is avoided. The size of the whole system is 25 mum times 1 mm. Simulation results show that the sampling rate reaches 4 MSa/s and the power dissipation of analog components is less than 300 muW while working.

The physics programme at the International Linear Collider (ILC) calls for a vertex detector (VD) providing unprecedented flavour tagging performances, especially for c-quarks and τ leptons. This requirement makes a very granular, thin and multi-layer VD installed very close to the interaction region mandatory. Additional constraints, mainly on read-out speed and radiation tolerance, originate from the beam background, which governs the occupancy and the radiation level the detector should be able to cope with. CMOS sensors are being developed to fulfil these requirements. This report addresses the ILC requirements (highly related to beamstrahlung), the main advantages and features of CMOS sensors, the demonstrated performances and the specific aspects of a VD based on this technology. The status of the main R&D directions (radiation tolerance, thinning procedure and read-out speed) are also presented.

Several development directions intended to adapt and optimize monolithic active pixel sensors for specific applications are presented in this work. The first example, compatible with the STAR microvertex upgrade, is based on a simple two-transistor pixel circuitry. It is suited for a long integration time, room-temperature operation and minimum power dissipation. In another approach for this application, a specific readout method is proposed, allowing optimization of the integration time independently of the full frame-readout time. The circuit consists of an in-pixel front-end voltage amplifier, with a gain on the order of five, followed by two analog memory cells. The extended version of this scheme, based on the implementation of more memory cells per pixel, is the solution considered for the outer layers of a microvertex detector at the international linear collider. For the two innermost layers, a circuit allowing fast frame scans together with on-line, on-chip data sparsification is proposed. The first results of this prototype demonstrate that the fixed pattern dispersion is reduced below a noise level of 15e−, allowing the use of a single comparator or a low-resolution ADC per pixel column. A common element for most of the mentioned readout schemes is a low-noise, low power consumption, layout efficient in-pixel amplifier. A review of possible solutions for this element together with some experimental results is presented.

We report on the performance of the MIMOSA8 chip. The chip is a 128/spl times/32 pixels array where 8 columns have analog direct outputs and 24 have discriminated outputs. The array is divided in four blocks of pixels with different conversion factors and is controlled by a serially programmable sequencer. MIMOSA8 is a representative of the CMOS sensors development option considered as a promising candidate for the vertex detector of the future International Linear Collider (ILC). The readout technique, implemented on the chip, combines high spatial resolution capabilities with high processing readout speed. Data acquisition, providing control of the chip and signal buffering and linked to a VME system, was made on the 8 analog outputs. Analog data, without and with a /sup 55/Fe X-ray source, were acquired and processed using off-line analysis software. From the reconstruction of pixel clusters, built around a central pixel, we deduce that the charge spread is limited to the closest 25 pixels and almost all the available charge is collected. The position of the total charge collection peak (and subsequently the charge-to-voltage conversion factor) stays unaffected when the clocking frequency is increased even up to 150 MHz (13.6 /spl mu/s readout time per frame). The discriminators, placed in the readout chain, have proved to be fully functional. Beam tests have been made with high energy electrons at DESY (Germany) to study detection efficiency.