GaN-on-diamond samples were demonstrated using a membrane-based technology. This was achieved by selective area Si substrate removal of areas of up to 1 cm × 1 cm from a GaN-on-Si wafer, followed by direct growth of a polycrystalline diamond using microwave plasma chemical vapor deposition on etch exposed N-polar AlN epitaxial nucleation layers. Atomic force microscopy and transmission electron microscopy were used to confirm the formation of high quality, void-free AlN/diamond interfaces. The bond between the III-nitride layers and the diamond was validated by strain measurements of the GaN buffer layer. Demonstration of this technology platform is an important step forward for the creation of next generation high power electronic devices.

This paper proposes a chemical pre-treatment process to reduce sulfate prior to atomic layer deposition of Al2O3 gate dielectrics on n-doped In0.7Ga0.3As layers to form metal oxide semiconductor capacitors (MOSCAPs). Cleaning with methanol was done after hydrogen chloride etching and ammonium sulfide passivation. X-ray photoelectron spectroscopy performed on the sample with methanol cleaning indicated that its native oxide regrowth was effectively prevented on the sulfur-passivated In0.7Ga0.3As surface under air exposure. By analysis using atomic force microscopy of the sample cleaned using methanol, no further increase of surface roughness was observed after 5 months of air exposure. In addition, a mid-gap interface defect density (D-it) of 1.3 x 10(12) cm(-2) eV(-1) was obtained from this sample. After forming gas annealing (FGA), the D-it was improved significantly, to a value below 10(12) cm(-2) eV(-1). The obtained data indicate that the combination of chemical pre-treatment and FGA is advantageous to passivating the trap states on In0.7Ga0.3As MOSCAPs. (C) 2019 The Electrochemical Society.

The results of an investigation into the impact of in situ H-2 plasma exposure on the electrical properties of the p/n-In-0.3 Ga-0.7 Sb-Al2O3 interface are presented. Samples were processed using a clustered inductively coupled plasma reactive ion etching and atomic layer deposition tool. Metal oxide semiconductor capacitors were fabricated subsequent to H-2 plasma processing and Al2O3 deposition, and the corresponding capacitance-voltage and conductance-voltage measurements were analyzed quantitatively via the simulation of an equivalent circuit model. Interface state (D-it) and border trap (N-bt) densities were extracted for samples subjected to the optimal process, with a minimum D-it of 1.73 x 10(12) eV(-1) cm(-2) located at similar to 110meV below the conduction band edge and peak N-bt approximately aligned with the valence and conduction band edges of 3 x 10(19) cm(-3) and 6.5 x 10(19) cm(-3), respectively. Analysis of the inversion response in terms of the extraction of the activation energy of minority carriers in inversion (p-type) and the observation of characteristics that pertain to minority carriers being supplied from an external inversion region (n-type) unequivocally demonstrate that the Fermi level is unpinned and that genuine surface inversion is observed for both doping polarities. Published under license by AIP Publishing.

In this work, a systematic study investigating the impact of in-situ H2 plasma exposure, at varying exposure powers and times, on the electrical properties of the interface between p/n-type In0.3Ga0.7Sb-Al;O3 is reported. It is found that the optimal process comprising H;2; plasma exposure and a forming gas anneal (FGA) is applicable to both p and n-type InGaSb gate stacks, with genuine surface inversion demonstrated for both. The Dit profile is extracted across the band gap with a value of 1.9 x 1012eV-1cm-2 obtained at mid gap.

Atomic layer deposition (ALD) is potentially a very suitable deposition technology to grow ultra thin films with excellent thickness control, good conformity on high aspect ratio structures, and less defects. Al2O3 and HfO2 are well-established high-k materials to replace SiO2 in transistor and capacitor applications. To grow high quality ALD films with low leakage current, high breakdown electric field and dielectric constant, it is important to understand the impact of both plasma enhanced ALD (PEALD) with O2-plasma and thermal ALD with H2O on the interface between ALD film and substrate surface, and also the impact of the interface on the quality of ALD films. We present the electrical and chemical characterizations of Al2O3 and HfO2 films directly grown on Au, Ti and TiN surfaces. Metal Insulator Metal (MIM) capacitors with 10nm of Al2O3 or 10nm of HfO2 as a dielectric layer were realized.

This study reports the impact of forming gas annealing (FGA) on the electrical characteristics of sulfur passivated, atomic layer deposited Al2O3 gate dielectrics deposited on (110) oriented n- and p-doped In0.53Ga0.47 As layers metal-oxide-semiconductor capacitors (MOSCAPs). In combination, these approaches enable significant Fermi level movement through the bandgap of both n- and p-doped In0.53Ga0.47 As (110) MOSCAPs. A midgap interface trap density (Dit) value in the range 0.87−1.8×1012 cm−2eV−1 is observed from the samples studied. Close to the conduction band edge, a Dit value of 3.1×1011 cm−2eV−1 is obtained. These data indicate the combination of sulfur pre-treatment and FGA is advantageous in passivating trap states in the upper half of the bandgap of (110) oriented In0.53Ga0.47 As. This is further demonstrated by a reduction in border trap density in the n-type In0.53Ga0.47 As (110) MOSCAPs from 1.8×1012 cm−2 to 5.3×1011 cm−2 as a result of the FGA process. This is in contrast to the observed increase in border trap density after FGA from 7.3×1011 cm−2 to 1.4×1012 cm−2 in p-type In0.53Ga0.47 As (110) MOSCAPs, which suggest FGA is not as effective in passsivating states close to the valence band edge.

This paper reviews some recent activity at the James Watt Nanofabrication Centre in the University of Glasgow in the area of plasma processing for energy efficient compound semiconductor-based transistors. Atomic layer etching suitable for controllable recess etching in GaN power transistors will be discussed. In addition, plasma based surface passivation techniques will be reviewed for a variety of compound semiconductor materials ((100) and (110) oriented InGaAs and InGaSb).

This paper reviews some recent activity at the James Watt Nanofabrication Centre in the University of Glasgow in the area of plasma processing for energy efficient compound semiconductor-based transistors. Atomic layer etching suitable for controllable recess etching in GaN power transistors will be discussed. In addition, plasma based surface passivation techniques will be reviewed for a variety of compound semiconductor materials ((100) and (110) oriented InGaAs and InGaSb).

This work presents, to the best of the authors knowledge, the first experimental findings on the impact of in situ H2 plasma exposure to the electrical properties of the interface between p-type Ga0.7In0.3Sb and atomic layer deposited Al2O3. The effects of trimethyl aluminium (TMA) exposure prior to Al2O3 deposition, and of a post gate metal forming gas anneal (FGA) are also investigated. The control sample, which was subjected to an ex situ HCl clean prior to ALD only, demonstrated a capacitance modulation of 36.29 % before FGA. This degraded for samples exposed to the H2 plasma for all plasma powers investigated. TMA exposure offered no improvement, and significantly increased the frequency dispersion in accumulation for all samples. A post gate metal FGA at 350 °C for 15 minutes was found to substantially improve the interface quality, with the capacitance modulation, frequency dispersion in accumulation and dC/dV improving by as much as 190 %, 91 %, and 170 % respectively. =

This work presents, to the best of the authors knowledge, the first experimental findings on the impact of in situ H2 plasma exposure to the electrical properties of the interface between p-type Ga0.7In0.3Sb and atomic layer deposited Al2O3. The effects of trimethyl aluminium (TMA) exposure prior to Al2O3 deposition, and of a post gate metal forming gas anneal (FGA) are also investigated. The control sample, which was subjected to an ex situ HCl clean prior to ALD only, demonstrated a capacitance modulation of 36.29 % before FGA. This degraded for samples exposed to the H2 plasma for all plasma powers investigated. TMA exposure offered no improvement, and significantly increased the frequency dispersion in accumulation for all samples. A post gate metal FGA at 350 °C for 15 minutes was found to substantially improve the interface quality, with the capacitance modulation, frequency dispersion in accumulation and dC/dV improving by as much as 190 %, 91 %, and 170 % respectively.

Based on sulphur passivation (10% (NH 4 ) 2 S, 20min), the interface of MOS capacitors between atomic-layer-deposited Al 2 O 3 and (110)-oriented p-type In 0.53 Ga 0.47 As layers indicate the capability of Fermi level movement and minority carrier inversion. C ox has effectively extracted by G m /ω & - ωdC/dω. Forming gas annealing (N 2 :H 2 5%:95% at 350°C, 30min) improves minority carrier response and the interface trap density around the midgap estimated to be 4.4×10 12 (1.6×10 12 ) cm -2 eV -1 before (and after) FGA. Moreover, Fowler-Nordheim (FN) tunneling current provides the conduction band offset at the surface between Al 2 O 3 and In 0.53 Ga 0.47 As (110)-oriented layer is ~1.81eV and the barrier height is estimated to be the same after FGA. Finally, the band parameter of Al 2 O 3 and In 0.53 Ga 0.47 As (110)-oriented layer has been firstly reported.

Based on current projections, III-Vs are expected to replace Si as the n-channel solution in FinFETs at the 7nm technology node. The realisation of III-V FinFETs entails top-down fabrication via dry etch techniques. Vertical fins in conjunction with high quality sidewall MOS interfaces are required for high-performance logic devices. This, however, is difficult to achieve with dry etching. Highly anisotropic etching required of vertical fins is concomitant with increased damage to the sidewalls, resulting in the quality of the sidewall MOS interface being compromised. In this work, we address this challenge in two stages by first undertaking a systematic investigation of dry etch processing for fin formation, with the aim of obtaining high resolution fins with vertical sidewalls and clean etch surfaces. In the second stage, dry etch process optimisation and post-etch sidewall passivation schemes are explored to mitigate the damage arising from anisotropic etching required for the realisation of vertical fins.