A precise, non-thermal, ultrashort pulsed laser process for selective and localized structural modification relevant to two-dimensional (2D) transition-metal-dichalcogenides (TMDs) ultra-thin films is reported. The approach enables site-specific pulsed laser annealing (SSPLA) and is shown to be effective in improving the electrical and structural properties of CVD-grown MoS2 thin film devices with precision and control. High spatial overlapping of laser pulses is employed to anneal regions of MoS2 thin films on SiO2-Si substrates using laser fluences less than 12 mJ cm-2 which is less than the threshold fluence for causing damage on surfaces. The process is implemented in ambient air at specific sites using laser beam scanning technology. Raman spectra confirm the conversion of amorphous to crystalline MoS2. The application of the site-specific annealing process confirms a reduction in actual MoS2 path resistance by up to a factor of four in devices. Cross sectional STEM confirms thinning and improvements to the degree of crystallization of partially crystallized films. AFM data indicates enlargement of isotropic grain structures with increasing fluence. The evidence suggests that crystallization occurs by local solid-state diffusion at low temperatures. The site-selective process is highly suitable for scalable precision back end of line processing in semiconductor wafer fabrication.

The challenging feat of both uniformly depositing and etching thin film materials can be overcome by the methods of atomic layer deposition (ALD) and atomic layer etching (ALE) with Angstrom level control. This study examines the deposition and etching of the transition metal oxide ZnO and doped variants ZnO:X incorporating Hf and Al as X in a 19:1 - Zn: metal ratio and the 2D transition metal dichalcogenide MoS 2 The studies were performed at the 200 mm full wafer scale employing a VEECO Fiji reactor system. For deposited MoS 2 a comparison between ALD and back end of line (BEOL) compatible chemical vapor deposition (CVD) films is also presented.[1] ZnO ALD produced polycrystalline Wurtzite material with a (100) preferred orientation. The growth rate was measured to be 1.86 Å per cycle, with a uniformity (after 500 cycles) of ~ 2% over a full 200 mm wafer. The measured resistivity (~8.5 X 10-3 Ω cm), mobility (~30 cm2·V−1·s−1) and carrier concentration (~2 x 1019 cm3) are typical of ALD grown nominally undoped ZnO. The isotropic ALE of nominally undoped ZnO proceeds at a linear etch rate (~0.29 Å) for 400 cycles albeit at a lower etch rate as compared to Mameli et al.. [2] Etch uniformity is shown to be ~ 5 % across the full 200 mm wafer. The electrical properties were unchanged by the etching process beyond a small degradation of resistivity (8.5 x10-3 to 1.5 x 10-2 Ω cm) after 400 cycles. The laminate doping of ZnO at a 19:1 ratio introduce complexity in the etching process, Under the same etching conditions both Al and Hf doped ZnO did not appear to significantly etch even after 400 cycles due to the formation of an etch barrier. Here we present first-principles atomic-level simulations, using density functional theory (DFT), observed physical properties (XRD, XPS, AFM, SKPFM), electrical data to elucidate the mechanism of etch and its retardation. The ALD of nominally undoped MoS 2 formed highly resistive polycrystalline material in both thermal and plasma enhanced modes, here we present methodologies for tuning the key parameters towards that of a viable 2D channel material and demonstrate ALE on both planar and high aspect ratio substrates. [1] Jun Lin et al 2021 2D Mater. 8 025008, DOI 10.1088/2053-1583/abc460 [2] A. Mameli, M. A. Verheijen, A. J. M. Mackus, W. M. M. Kessels, and F. Roozeboom. ACS Applied Materials & Interfaces 2018 10 (44), 38588-38595

Oxide defects in the high-k/InGaAs MOS system are investigated. The behaviour of these traps is explored from room temperature down to 10K. This study reveals that the exchange of free carriers between oxide states and either the conduction or the valence band is strongly temperature dependant. The capture and emission of electrons is strongly suppressed at 10K as demonstrated by the collapse of the capacitance frequency dispersion in accumulation for n-InGaAs MOS devices, though hysteresis in the C-V sweeps is still present at 10K. Phonon assisted tunnelling processes are considered in the simulation of electrical characteristics. The simulated data match very well the experimental characteristics and provide energy and spatial mapping of oxide defects. The multi phonon theory also help explain the impedance data temperature dependence. This study also reveals an asymmetry in the free carrier trapping between n and p type devices, where hole trapping is more significant at 10K.

A hot-electron transistor（HET） is a unipolar and majority carrier device with voltage-controlled transport of ballistic hot electrons,and the monochromatic high-energy hot electrons are afforded by the tunnel and filter oxide barriers.The injected hot electrons from the emitter transit through the tunnel barrier with a width below the carrier mean free path（MFP） into the base region and then cross the filter barrier and are finally collected by the collector.

Tailoring MoS 2 into nanoribbon (NR) provides an efficient regulation of the electrical property. Herein, high-performance MoS 2 transistors are fabricated by optimizing the channel height, width, and length. The electrical performance of the device is improved due to enhanced gate modulation capability from the quasi-3D channel geometry. The devices obtain a high ON-state current of $496 ~\mu \text{A}\,\cdot \, \mu \text{m}$ −1 while offering appropriate field-effect mobility of 52.6 cm 2 V −1 s −1 as the height and width of MoS 2 NR are fixed to 20 ± 3 nm and 130 ± 10 nm, respectively. The high performance and desirable current saturation are promising to construct robust logic gates. The NOT and NAND gates are assembled based on an individual MoS 2 NR. The inverters demonstrate a voltage gain of −17.8 and a total noise margin of nearly 75%. This work provides an alternative strategy to fully take the advantage of 2-D materials in logic electronics circuits.

2-D materials are promising for future advanced electronics beyond silicon due to their intrinsic ultrathin body for enhanced electrostatic gate control. Herein, an omega-shaped dual-gated MoS 2 transistors based on Ag nanowire (NW) as buried gate are fabricated, and the omega-shaped gate architecture enables enhanced local gate controllability, leading to excellent electrical performance with an ON-/ OFF-current ratio of 10 8 and a subthreshold swing (SS) of 76 mV/dec at room temperature. By controlling the threshold voltage of the transistor with dual gate, an inverter and a NAND gate circuit are fabricated, and the voltage gain of inverters is 36 with high noise margin of 87% ${V}_{{\text{DD}}}$ . This work demonstrates an avenue for high-current MoS 2 transistors.

The fundamental Boltzmann limitation dictates the ultimate limit of subthreshold swing (SS) to be 60 mV dec-1 , which prevents the continued scaling of supply voltage. With atomically thin body, 2D semiconductors provide new possibilities for advanced low-power electronics. Herein, ultra-steep-slope MoS2 resistive-gate field-effect transistors (RG-FETs) by integrating atomic-scale-resistive filamentary with conventional MoS2 transistors, demonstrating an ultra-low SS below 1 mV dec-1 at room temperature are reported. The abrupt resistance transition of the nanoscale-resistive filamentary ensures dramatic change in gate potential, and switches the device on and off, leading to ultra-steep SS. Simultaneously, RG-FETs demonstrate a high on/off ratio of 2.76 × 107 with superior reproducibility and reliability. With the ultra-steep SS, the RG-FETs can be readily employed to construct logic inverter with an ultra-high gain ≈2000, indicating exciting potential for future low-power electronics and monolithic integration.

Two-dimensional molybdenum disulfide (MoS 2 ) is a potential alternative channel material to silicon for future scaled transistors. Scaling down the gate dielectric and maintaining a high-quality interface is challenging with such materials, because the atomic thickness of MoS 2 makes it sensitive to defects common in amorphous gate oxides such as hafnium oxide (HfO x ). Here we show that a van der Waals gap of 5.3 Å can be formed between HfO x and MoS 2 via the ozone treatment of a hafnium disulfide (HfS 2 )/MoS 2 stack. The ozone treatment converts the HfS 2 flake into a HfO x dielectric, and excess oxygen accumulation at the interface widens the van der Waals gap. Experimental results and density functional theory calculations show that the increased gap decouples the interaction between the HfO x dielectric and MoS 2 channel, allowing the intrinsic properties of the MoS 2 semiconductor to be preserved. The resulting MoS 2 van der Waals-gap-gated transistors exhibit a negligible hysteresis of 10 mV and average subthreshold slope of 63.1 mV dec −1 , which is close to the physical Boltzmann limit of 60.0 mV dec −1 . We also show that the transistors can be used to construct NOT, OR and AND logic gates.

In the past few years, ambipolar tin monoxide (SnO) thin-film transistors (TFTs) have been widely studied because of ever-increasing demands for simplifying CMOS circuit and fabrication of more compact CMOS devices. However, in view of the serious decline in device performance upon gate-bias stress and environmental exposure, it is urgent to develop an effective passivation strategy for improving the operational stability of SnO TFTs. Here, aluminum oxide (Al 2 O 3 )/hafnium oxide (HfO 2 ) bilayer dielectric is employed as a passivation layer for achieving ambipolar SnO TFTs with greatly enhanced operational stability, in which the Al 2 O 3 dielectric is used to reduce the interfacial trap states, while HfO 2 dielectric can prevent the diffusion of water/oxygen. Furthermore, a complementary-like inverter is presented by simply connecting two identical ambipolar SnO TFTs, which can be maintained in ambient condition for more than four months with a voltage gain exceeding 30. The capacity to synchronously achieve field-effect conversion, operational stability, as well as logic function in ambipolar SnO TFTs opens up a rational avenue to the realization of compact logic circuits.

III-V RF devices operating at cryogenic temperature are highly desirable for application areas such as space communication or quantum computing. In the case of quantum computation, integration of the readout and control electronics close to the quantum bit (Qubit) stage is needed to allow scaling of the number of Qubits needed for practical applications. Many characteristics of high frequency operation at cryogenic temperature in novel III-V devices are not fully understood. In this study, we will focus on the behaviour of defects at or near the interface between the high dielectric constant (high-k) oxide and InGaAs semiconductor at cryogenic temperature and how it may affect the full device operation at low temperature. The thermal budget constraints associated with the processing III-V semiconductor devices prohibit the use of high temperature thermal treatments to reduce oxide defect densities in the high-k. This leads to defective oxides presenting higher instability, variability, and degradation issues than in the Si/SiO2 system. The methods developed to investigate defects in the Si/SiO2 metal oxide semiconductor (MOS) system generally attribute the divergence in capacitance voltage (CV) and conductance voltage (GV) from the ideal CV and GV characteristics mostly to interface state defects (ITs) [1], which is not the case of the III-V MOS system. As a consequence, attempts to fit the multi-frequency CV and GV response of III-V MOS structures in the weak inversion regime, using interface states alone, cannot recreate the experimental data. In this study, we present an advanced MOS defects characterisation method capable of discerning between the contributions of oxide defects (sometimes labelled ‘border traps’) and ITs. The method relies on the fully physics based simulation of MOS systems, including inelastic tunnelling from the semiconductor to localized defects in the oxide [2] to reproduce the experimental multi-frequency CV and GV characteristics. The simulations include physical models accurately describing the carrier capture/emission processes by oxide traps, and which incorporate tunneling into the dielectric in conjunction with lattice relaxation at the interface/border trap sites [3, 4]. The results will show that the simulations are able to reproduce the room temperature experimental data (both CV and GV) of InGaAs/Al2O3 MOS structures in all bias regions. This new method enables the precise extraction of the density, energy and spatial distribution away from the interface of electrically active oxide defects from different experimental results. Results will also be presented showing how the multi-frequency CV and GV response of n-InGaAs/Al2O3 and p-InGaAs/Al2O3 MOS structures change with reducing temperature. Measurements at 223K show a marked reduction in the CV and GV dispersion with frequency in the accumulation and depletion regions, consistent with a phonon assisted tunnelling interaction of electrons and holes with defects in the Al2O3. Reduction in the measurement temperature to 10K still demonstrates a residual dispersion of the capacitance and conductance with frequency, which is more marked in the case of the p-InGaAs/Al2O3 MOS structure. The models and trap distributions extracted from room temperature will be applied to the reduced temperature measurements (233 K and 10 K) to investigate the validity of the models and to gain further understanding of defect behaviour and associated device implications at cryogenic temperatures. [1] E. H. Nicollian and J. R. Brews, “MOS Physics and Technology,” John Wiley & Sons, New York, 1982. [2] A. Palma, et al. Phys. Rev. B Condens. Matter Mater. Phys., 56 (15), pp. 9565-9574 (1997). [3] E. Caruso, et al. IEEE Trans. Electron Devices, 67 (10), pp. 4372-4378 (2020) [4] G. Sereni, et al. “IEEE Trans. Electron Devices, vol. 62, no. 3, pp. 705–712, (2015).

Silicon-based heterojunction (SHJ) solar cells demonstrate high efficiencies over their homojunction counterparts, revealing the potential of such technologies. We present here the first steps towards the development of molybdenum disulfide (MoS2)/c-silicon heterojunction solar cells, consisting of a preliminary study of the MoS2 material and numerical device simulations of MoS2/Si heterojunction solar cells, using SILVACO ATLAS. Through the optical and structural characterization of MoS2/SiO2/Si samples, we found a significant sensitivity of the MoS2 to ambient oxidation. Optical ellipsometry showed a bandgap of 1.87 eV for a 7 monolayer thick MoS2 sample, suitable for the targeted application. Finally, we briefly introduce a device simulation and show that the MoS2/Si heterojunction could lead to a gain in quantum efficiency, especially in the region with short wavelengths, compared with a standard a-Si/c-Si solar cell.

2D semiconductors present tunable property with the physical dimension. Herein, an efficient strategy to modulate the band structure of ultrathin channel by dimension tailoring of the 2D materials is reported. In order to verify the practicability of this strategy, bulk‐MoS 2 /MoS 2 nanoribbon (NR) homojunctions are constructed with a rectification ratio approaching up to 10 4 and an ideality factor of 1.77 which readily enable the fabrication of MoS 2 ‐based metal‐semiconductor field‐effect transistors, and the bulk‐MoS 2 and the MoS 2 NR serve as gate and channel, respectively. The fabricated devices exhibit robust performance, such as high saturation current of 46 µA·µm −1 and high on–off ratio over 5 × 10 5 at room temperature. The output current presents a high value of 140 µA·µm −1 at 77 K, then decreases with temperature. Moreover, the fabricated inverter provides a voltage gain of 15.4 and a near‐ideal noise margin of 83% of supply voltage. This strategy indicates an alternative way to construct transistors based on the derivative of the same 2D material.

A manufacturing-compatible 300 mm chamber reactor for atomic layer deposition or chemical vapour deposition, and pre-fitted with H 2 /H 2 S gases that can be uniformly delivered to the wafer surface, is employed to thermally convert Pt to PtS in a H 2 /H 2 S gaseous atmosphere for 7 hours at a chamber temperature of 550 degrees C. Prior to conversion, platinum layers 5 nm thick are uniformly deposited by electron beam evaporation onto -30 nm of amorphous aluminium sesquioxide deposited by atomic layer deposition on, (a) p -type silicon, and (b) c-plane sapphire. Structural characterisation is performed by high-resolution cross-sectional transmission-electron microscopy, scanning-electron microscopy and Raman spectroscopy, confirming the formation of continuous films of polycrystalline platinum monosulfide (PtS) with a -15 nm thickness. Electrical characterisation is performed by 4-point resistivity and Hall-effect transport measurements on van der Pauw structures of PtS on aluminium sesquioxide on c-plane sapphire, and by back-gate junctionless MOSFET device measurements for PtS on aluminium sesquioxide on p -type silicon, showing that PtS behaves as a semiconductor with a mobility of -16 cm 2 /V.s and with an n -type carrier concentration of -1.2 x 10 15 cm -3 . Advanced commercial-grade Sentaurus simulations, alongside density-functional theory calculations, agree well with the experimental observations and suggest a large bandgap of -1.58 eV may be possible that could lead to a low off-current and a high I on /I off ratio, suggesting that PtS may be an advanced material candidate for future device integration with CMOS and for 3D integration applications in Beyond-CMOS and More-than-Moore technologies. (c) 2021 The Author(s). Published by Elsevier Ltd. This is an open access article under the CC BY license ( http://creativecommons.org/licenses/by/4.0/ )

Direct growth of transition metal dichalcogenides over large areas within the back-end-of-line (BEOL) thermal budget limit of silicon integrated circuits is a significant challenge for 3D heterogeneous integration. In this work, we report on the growth of MoS2 films (similar to 1-10 nm) on SiO2, amorphous-Al2O3, c-plane sapphire, and glass substrates achieved at low temperatures (350 degrees C-550 degrees C) by chemical vapor deposition in a manufacturing-compatible 300 mm atomic layer deposition reactor. We investigate the MoS2 films as a potential material solution for BEOL logic, memory and sensing applications. Hall-effect/4-point measurements indicate that the similar to 10 nm MoS2 films exhibit very low carrier concentrations (10(14)-10(15) cm(-3)), high resistivity, and Hall mobility values of similar to 0.5-17 cm(2) V-1 s(-1), confirmed by transistor and resistor test device results. MoS2 grain boundaries and stoichiometric defects resulting from the low thermal budget growth, while detrimental to lateral transport, can be leveraged for the integration of memory and sensing functions. Vertical transport memristor structures (Au/MoS2/Au) incorporating similar to 3 nm thick MoS2 films grown at 550 degrees C (similar to 0.75 h) show memristive switching and a stable memory window of 10(5) with a retention time >10(4) s, between the high-low resistive states. The switching set and reset voltages in these memristors demonstrate a significant reduction compared to memristors fabricated from pristine, single-crystalline MoS2 at higher temperatures, thereby reducing the energy needed for operation. Furthermore, interdigitated electrode-based gas sensors fabricated on similar to 5 nm thick 550 degrees C-grown (similar to 1.25 h) MoS2 films show excellent selectivity and sub-ppm sensitivity to NO2 gas, with a notable self-recovery at room temperature. The demonstration of large-area MoS2 direct growth at and below the BEOL thermal budget limit, alongside memristive and gas sensing functionality, advances a key enabling technology objective in emerging materials and devices for 3D heterogeneous integration.

Vertical transistors—in which the channel length is determined by the thickness of the semiconductor—are of interest in the development of next-generation electronic devices. However, short-channel vertical devices are difficult to fabricate, because the high-energy metallization process typically results in damage to the contact region. Here we show that molybdenum disulfide (MoS 2 ) vertical transistors with channel lengths down to one atomic layer can be created using a low-energy van der Waals metal integration technique. The approach uses prefabricated metal electrodes that are mechanically laminated and transferred on top of MoS 2 /graphene vertical heterostructures, leading to vertical field-effect transistors with on–off ratios of 26 and 10 3 for channel lengths of 0.65 nm and 3.60 nm, respectively. Using scanning tunnelling microscopy and low-temperature electrical measurements, we show that the improved electrical performance is the result of a high-quality metal–semiconductor interface, with minimized direct tunnelling current and Fermi-level pinning effect. The approach can also be extended to other layered materials (tungsten diselenide and tungsten disulfide), resulting in sub-3-nm p-type and n-type vertical transistors.

Two-dimensional (2D) semiconductors have attracted considerable attention in recent years. However, to date, there is still no effective approach to produce large-scale monolayers while retaining their intrinsic properties. Here, we report a simple mechanical exfoliation method to produce large-scale and high-quality 2D semiconductors, by designing an atomically flat Au-mesh film as the peeling tape. Using our prefabricated mesh tape, the limited contact region (between the 2D crystal and Au) could provide enough adhesion to mechanically exfoliate uniform 2D monolayers, and the noncontact region (between the mesh holes and monolayers) ensures weak interaction to mechanically release the 2D monolayers on desired substrates. Together, we demonstrate a scalable method to dry exfoliate various 2D monolayer arrays onto different substrates without involving any solutions or contaminations, representing the optimization between material yield, scalability, and quality. Furthermore, detailed optical and electrical characterizations are conducted to confirm their intrinsic quality. With the ability to mechanically exfoliate various 2D arrays and further restacking them, we have demonstrated large-scale van der Waals heterostructure arrays through layer-to-layer assembling. Our study offers a simple and scalable method for dry exfoliating 2D monolayer and heterostructure arrays with intrinsic material quality, which could be crucial to accelerate fundamental investigations as well as practical applications of proof-of-concepts devices.

The ever-decreasing size of transistors requires effectively electrostatic control over ultra-thin semiconductor body. Rational design of the gate configuration can fully persevere the intrinsic property of two-dimensional (2D) semiconductors. Here we design and demonstrate a 2D MoS2 transistor with omega-shaped gate, in which the local gate coupling is enhanced by the non-planar geometry. The omega-shaped non-planar transistors exhibit a high current of 0.89 A/μm and transconductance of 32.7 μS/μm. The high performance and desirable current saturation promise the construction of robust logic gate. The inverters show a voltage gain of 26.6 and an ideal total margin nearly 89%. We also assemble NOT-AND (NAND) gate on an individual MoS2 flake, and the constructed NAND gate demonstrates the universal functionality of the transistors as well. This work provides an alternative strategy to fully take the advantages of 2D materials for high-performance field-effect transistors.

Construction of in-plane p-n junction with clear interface by using homogenous materials is an important issue in two-dimensional transistors, which have great potential in the applications of next-generation integrated circuit and optoelectronic devices. Hence, a controlled and facile method to achieve p-n interface is desired. Molybdenum sulfide (MoS2) has shown promising potential as an atomic-layer n-type semiconductor in electronics and optoelectronics. Here, we developed a facile and reliable approach to in-situ transform n-type MoS2 into p-type MoO3 to form lateral p-n junction via a KI/I2 solution-based chemical oxidization process. The lateral MoS2/MoO3 p-n junction exhibits a highly efficient photoresponse and ideal rectifying behavior, with a maximum external quantum efficiency of ∼650%, ∼3.6 mA W−1 at 0 V, and a light switching ratio of ∼102. The importance of the built in p-n junction with such a high performance is further confirmed by high resolution photo current mapping. Due to the high photoresponse at low source-drain voltage (VDS) and gate voltage (VG), the formed MoS2/MoO3 junction p-n diode shows potential applications in low-power operating photodevices and logic circuits. Our findings highlight the prospects of the local transformation of carrier type for high-performance MoS2-based electronics, optoelectronics and CMOS logic circuits.

This work demonstrates that when inelastic tunneling between oxide traps and semiconductor bands is considered, the traps with energy aligned to the semiconductor bandgap play a significant role in the frequency dispersion of the capacitance-voltage (C-V) and conductance-voltage (G-V) characteristics of metal-oxide-semiconductor (MOS) systems. The work also highlights that a nonlocal model for tunneling into interface states is mandatory to reproduce experiments when carrier quantization in the inversion layer is accounted for. A model, including these ingredients, is used to evaluate the energy and depth distribution of oxide traps in a n-In0.53Ga0.47As/Al2O3 MOS system and is able to accurately fit the C-V frequency dispersion from depletion to weak inversion. The oxide trap distribution determined from the C-V response predicts the corresponding G-V dispersion with frequency.