An analytical compact model for tunnel field-effect transistor (TFET) circuit simulation is extended by adding a gate tunnel current model, a charge-based capacitor model, and a noise model. The equation set is broadly applicable across materials systems and TFET geometries and is readily fitted to rigorous physics-based device simulations and experimental results. To validate the gate current and charge models, technology computer-aided design (TCAD) simulations of a GaN/InN/GaN TFET are used. TCAD simulations show that the gate tunneling current depends on the gate-drain bias with a 100%/0% drain/source current partition. Terminal capacitances evaluated from the charge model agree well with simulations. The model is implemented in Verilog-A and the significance of gate current in the circuit design is illustrated in an amplifier design.

Quantum transport simulations are performed in tunneling FETs (TFETs) with the gate electric field in-line with the tunneling junction direction (in-line TFETs). Charge self-consistency and thermalization effects are included in a semiclassical Poisson solution to compute the electrostatic potential. The obtained potential is then used for current calculation with the ballistic nonequilibrium Green's function method (NEGF) in the tight binding basis. It is shown that the NEGF method predicts a higher subthreshold swing than the often-used dynamic nonlocal (DNL) path band-to-band method. The NEGF method accounts for the direct source-drain tunneling, which is underestimated in the DNL path approach in the studied geometries. Undercut is shown to be essential to obtain switching slope below 60 mV/decade in the in-line TFETs.

The concept and simulated device characteristics of tunneling field-effect transistors (TFETs) based on III-nitride heterojunctions are presented for the first time. Through polarization engineering, interband tunneling can become significant in III-nitride heterojunctions, leading to the potential for a viable TFET technology. Two prototype device designs, inline and sidewall-gated TFETs, are discussed. Polarization-assisted p-type doping is used in the source region to mitigate the effect of the deep Mg acceptor level in p-type GaN. Simulations indicate that TFETs based on III-nitride heterojunctions can be expected to achieve ON/OFF ratios of 106 or more, with switching slopes well below 60 mV/decade, ON-current densities approaching 100 μA/μm, and energy delay products as low as 67 aJ-ps/μm.

A physics-based analytic model of the ON- and OFF-currents in a homojunction tunnel field-effect transistor (TFET) is used to understand the relationship between bandgap, gate length, ON-current, OFF-current, ON/OFF current ratio, and supply voltage to meet minimum energy requirements. The model, which applies to direct-bandgap semiconductors, is validated against numerical simulations to show that it captures the trends of more comprehensive simulations. The analytic model is then used to compare alternative channel materials for TFETs. Gate-all-around InAs nanowire and graphene nanoribbon TFETs are used as design examples at gate lengths of 10 and 15 nm and for an ON/OFF current specification of 105. The results suggest that TFETs based on 2-D materials can be more energy efficient than semiconductor nanowire TFETs and conventional metal-oxide-semiconductor field-effect transistors for low-power logic.

Crosswind effect on the cooling performance of large natural draft dry cooling towers (NDDCT) has been verified to be unfavourable by many researchers. Small size natural draft cooling towers (height <30m) proposed for geothermal and other renewable power plants are expected to be more negatively affected. CFD modelling has been carried out to numerically analyse the heat transfer performance of a 15m-high small NDDCT under different crosswind speeds. Simulations show that, at certain crosswind speeds, the crosswind significantly degrades the cooling performance. However, the negative effect of the crosswind can be turned into positive in small natural draft cooling towers by introducing windbreak walls that guide the air mobilised by crosswind through the heat exchangers. When windbreak walls are used, the results show that the tower performance improves with increased crosswind velocity.

A numerical model that accurately describes interband tunneling in backward diodes and broken-gap tunnel diode structures based on the InAs/GaSb material system is described. The model applies the transfer matrix method to discretized bias-dependent energy band profiles to calculate the transmission probability for tunneling. The model has been validated against experimental results, with good agreement in the current-voltage and curvature coefficient having been obtained for a range of heterostructure backward diode and interband tunnel diode structures. (C) 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim

In this paper we show that tunnel field effect transistors (TFETs) biased in the subthreshold region promise several advantages for low-power/high-frequency analog IC applications (e.g. GHz operation with sub-0.1 mW power consumption). Analytical and TCAD models for graphene nano-ribbon (GNR) and InAs/GaSb nanowire TFETs are employed, respectively, for the first time in subthreshold analog circuit examples using the gm/Id integrated circuit (IC) design technique. From comparison of these TFET technologies with traditional FETs it is observed that due to the higher currents per unit gate width at low voltage for TFETs, smaller, higher speed, and lower power analog circuits are enabled.

The first fabrication of a III-V tunnel field-effect transistor (TFET) with tunneling directed perpendicular to the gate is reported. This new transistor geometry utilizes an InAs/Al0.45Ga0.55Sb staggered-gap tunnel junction intended for high on current and steep subthreshold swing. The first measurements of the transistor transport properties at room temperature and -50 °C are provided. Tunneling transport is confirmed by the observation of negative differential resistance in the tunnel junction in the forward bias polarity. Transistor on-current of 21 μA/μm at 0.3 V and subthreshold swing of 830 mV/decade is found. The large subthreshold swing is consistent with the large density of interface traps at the oxide/semiconductor interface (© 2012 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

The current-voltage characteristics of AlGaSb/InAs staggered-gap n-channel tunnel field-effect transistors are simulated in a geometry in which the gate electric field is oriented to be in the same direction as the tunnel junction internal field. It is shown that this geometry can also support low-voltage operation and low subthreshold swing. In the absence of a simple analytic theory for this transistor to allow direct analytic comparisons, two-dimensional numerical simulations are used to explore the electrostatic and geometrical design considerations including dependence on gate length, gate underlap, gate undercut, and equivalent oxide thickness.

Vertical n-channel tunnel field-effect transistors (TFETs) with tunneling normal to the gate based on an n+ In ∞=0.53->;1 GaAs/p + InP heterojunction have been demonstrated to exhibit simultaneously a high I ON /I OFF ratio of 6 × 10 5 , a minimum subthreshold swing (SS) of 93 mV/dec, and an on-current of 20 μA/μm at V DS = 0.5 V and a gate swing of 1.75 V at 300 K, a record TFET performance. The significant improvement in device performance is ascribed to the adoption of a thin equivalent oxide thickness (EOT) of ~1.3 nm for improved electrostatics and the use of plasma-enhanced chemical vapor deposition SiN ∞ mesa passivation to preserve the integrity of the thin exposed semiconductor layers.

Record high on-current of 78 mu A/mu m in a tunnel field-effect transistor (TFET) is achieved at 0.5 V at room temperature. The TFET employs a staggered AlGaSb/InAs heterojunction with the tunneling direction oriented in-line with the gate field. The measured results are consistent with numerical simulation of the device structure. Simulations of optimized structures suggest that switching speed comparable to that of the MOSFET should be achievable with improvements in the source and drain resistances.

A relatively simple and self-aligned vertical tunneling field-effect transistor (VTFET) process has been demonstrated using In0.53Ga0.47As/InAs/InP heterojunctions. At 300 K, the VTFETs show an on-current of 3 – 4.8 μA/μm and a minimum subthreshold swing (SS) of 220 mV/dec using Al2O3 gate oxide. The corresponding tunneling diodes exhibit negative differential resistance under forward bias over a range of temperatures, which confirms that the conduction mechanism is indeed band-to-band tunneling. This new self-aligned process is attractive to quickly realize and test VTFET designs.

Current progress in the development of compound semiconductor tunnel field-effect transistors (TFETs) for low-voltage, high performance logic applications is reviewed.

Vertical n-channel tunnel field-effect transistors (FETs) based on compound semiconductors, in a new geometry with tunneling normal to the gate, are demonstrated for the first time using an n+ In0.53Ga0.47As/n+ /n+,=0.53- >;1 GaAs/p+ InP heterojunction. At 300 K, the TFETs show an on-current of ~20 μA/μm and a minimum subthreshold swing (SS) of 130 mV/dec using an Al2O3 gate dielectric (EOT ~3.4 nm). Postdeposition annealing of the gate dielectric improves SS, and device passivation using atomic layer deposition can effectively prevent degradation of drain current over time. The clear negative differential resistance (NDR) observed in the tunnel junction and the trend toward NDR in the TFETs confirm that the transport mechanism in these FETs is interband tunneling.

A general solution for the electrostatic potential in an atomic-thin-body (ATB) field-effect transistor geometry is presented. The effective electrostatic scaling length, {\lambda}eff, is extracted from the analytical model, which cannot be approximated by the lowest order eigenmode as traditionally done in SOI-MOSFETs. An empirical equation for the scaling length that depends on the geometry parameters is proposed. It is shown that even for a thick SiO2 back oxide {\lambda}eff can be improved efficiently by thinner top oxide thickness, and to some extent, with high-k dielectrics. The model is then applied to self-consistent simulation of graphene nanoribbon (GNR) Schottky-barrier field-effect transistors (SB-FETs) at the ballistic limit. In the case of GNR SB-FETs, for large {\lambda}eff, the scaling is limited by the conventional electrostatic short channel effects (SCEs). On the other hand, for small {\lambda}eff, the scaling is limited by direct source-to-drain tunneling. A subthreshold swing below 100mV/dec is still possible with a sub-10nm gate length in GNR SB-FETs.

On the ITR.S roadmap, the physical gate length, LG, has been rapidly scaling down, and will reach values below ~ 10nm beyond 2020. The single-gate (SG) extremely thin SOI (ETSOI) MOSFET, the double-gate (DG) FinFET, and the gate-all-around (GAA) Si nanowire (SiNW) MOSFET geometries may facilitate such scaling. Nevertheless, sub-10nm Lα scaling will be a great challenge because of the significant mobility degradation and channel thickness variations in the aforementioned geometries with a few-nanometer body thicknesses as required by electrostatic short-channel considerations. Therefore, new device geometries and technologies are required that could simultaneously maintain the electrostatic integrity and the superior transport properties for sub-lOnm Lα scaling. It has been recently shown that the atomic-thin-body (ATB) geometry can meet the electrostatic requirements for LG <; 10nm. At the ATB limit, carbon electronics based on graphene nanoribbons (GNRs) with tunable band gaps have been widely considered for high-performance digital electronics. Here, ballistic transport of GNR Schottky-barrier (SB) FETs is simulated self-consistently, including both thermionic emission and tunneling. We show the better gate length scalability of GNRs compared to Si MOSFETs, even though significant material related challenges will have to be overcome. Lα scaling below 10nm is mainly limited by direct source-to-drain tunneling and the ambipolar effect in the off-state, which can be suppressed by narrower ribbon widths (of the order ~ 10nm), and larger effective masses obtained from band structure engineering. If a negative metal-graphene SB-height could be achieved, the GNR SB-FET could operate without significant series resistance effects, and deliver high on-current (ION ). The performance of the ultimate GNR SB-FETs is comparable to the MOSFET targets of the ITRS roadmap.

Tunneling field-effect transistors (TFETs) are attracting a lot of interest because of their potential to reduce power dissipation in logic applications. Performance of TFETs is expected to improve with increasing electrostatic control as provided by ultra-thin body (UTB) based single-gate (SG), double-gate (DG), and nanowire based gate-all-around (GAA) structures. Increasing geometrical confinement, however, could also lead to significant quantum confinement effects, especially in III-V materials, which is detrimental to TFET performance. A previous study compared the operation of lnAs based SG, DG, and GAA TFETs using quantum transport simulations. Because of the use of the tight-binding model for the device structure, however, the important tradeoff between electrostatics vs. quantum confinement in different geometries could not be clearly distinguished. In this work, we use detailed analytical calculations to compare the operation of SG, DG, and GAA TFETs in InAs, and examine the competing effects of electrostatics vs. quantum confinement. We demonstrate an important tradeoff between the superior electrostatic control vs. current injection efficiency in TFETs with increasing lateral confinement, which will be an essential consideration for future TFET design.

In this work, the lateral InGaAs tunnel FET is configured and sized to enable gate control of the Zener (reverse bias) tunneling current. The p+InGaAs transistor channel is 4 nm thick with a n+p+ source injector and a thin 3/3 nm HfO2/Al2O3 high-k gate dielectric. Atomic-layer deposition (ALD) is used to deposit the gate dielectric.