Fin field-effect transistor (FinFET) technology has been introduced to the mainstream complementary metal-oxide semiconductor (CMOS) manufacturing for low-power and high-performance applications. However, advanced FinFET nodes are facing significant challenges to enhance the device performance due to the increasingly prominent parasitic resistance and capacitance. In this study, for the first time, we demonstrate methods of enhancing p-channel FinFET (pFET) performance on a fully integrated advanced FinFET platform via source/drain (S/D) cavity structure optimization. By modulating the cavity depth and proximity around the optimal reference point, we show that the trade-off between the S/D resistance and short channel effect, as well as the impact on the parasitic capacitance must be considered for the S/D cavity structure optimization. An extra process knob of applying cavity implant on the desired cavity structure was also demonstrated to modify the S/D junction profile for device performance enhancement.

设计了一种易于集成、适用于驱动高侧N型开关管的栅极驱动器,该电路具有成本低、速度快、驱动能力强等特点,可以满足大尺寸高侧N型开关管的驱动需求.内置的、可持续工作的电荷泵能够驱动高侧N型开关管,使之恒定导通,解决了传统自举电路中低侧开关管不工作时高侧开关管输出电压不稳定的问题.该方案无需使用外置的自举电容,降低了栅极驱动器的使用成本和封装成本.采用0.18 μm BCD工艺进行设计,并成功流片.测试结果表明,该栅极驱动器可以驱动面积达0.5 mm2的高侧N型开关管,电路可靠性高.

Low-dielectric constant (low-k) material is critical for advanced FinFET technology parasitic capacitance reduction to enable low-power and high-performance applications. Silicon Oxycarbonnitride (SiOCN) is one of the most promising low-k materials for FinFET gate sidewall spacer. The k value of SiOCN can be controlled in the range of 4.1-5.2 by modifying the chemical contents during the deposition process. However, the integration of SiOCN with k value lower than 5.2 for advanced FinFET technology faces substantial challenges associated with the material damage from subsequent manufacturing processes. Here, the authors demonstrate a hybrid low-k spacer scheme on a fully integrated 7 nm FinFET technology platform, in which SiOCN with k value of 4.5 was successfully integrated along the sidewalls of the gate electrode as spacer while retaining the structural integrity and dielectric properties. Device characterisation on the hybrid low-k spacer scheme (k = 4.5) demonstrated 12/11% reduction in P/NFET overlap capacitance (C-OV) and 3% reduction in ring oscillator effective capacitance (C-EFF) in comparison to the baseline reference using SiOCN with k value of 5.2 as spacer. Furthermore, reliability characterisation confirmed the dielectric breakdown voltage (V-BD) and leakage current (I-LKG) of the hybrid low-k spacer (k = 4.5) were comparable to the baseline reference (k = 5.2), meeting the technology requirements.

A combined wet and dry cleaning process for GaN(0001) has been investigated with XPS, capacitance voltage measurement. Capacitance–voltage characterization showed that combined ex-situ wet sulfide passivation and in-situ cyclic trimethylaluminum (TMA)/hydrogen plasma exposure led to reductions in the densities of both interface traps and border traps. In situ XPS studies show that after the wet sulfur treatment on GaN(0001), sulfur desorbs in vacuum at 25C prior to gate oxide deposition. Ex-situ depth profiling ARXPS post-ALD deposition shows that the a-Al2O3 gate oxide bonds directly to the GaN substrate leaving both the gallium surface atoms and the oxide interfacial atoms with bulk-like charge. DFT calculations predict that the oxide/GaN(0001) interface will have bulk-like charges and a low density of band gap states. This passivation is consistent with the oxide restoring the surface gallium atoms to tetrahedral bonding by eliminating the gallium empty dangling bonds on bulk terminated GaN(0001). A key application of gate oxide on GaN is GaN tunnel FETs. Tunneling FETs (TFETs) are one promising option for reducing power consumption per logic function due to their potential for subthreshold slopes steeper than the thermionic limit of 60 mV/decade. While TFETs based on narrow-gap semiconductors have been demonstrated, the narrow band gaps of these materials also lead to limited on-off current ratios, compromising their power efficiency. GaN-based TFETs offer a potential solution to this problem, since the large band gap effectively reduces off-state current, and the large polarization fields present in III-N heterostructures (which arise from the lack of inversion symmetry in the wurtzite crystal structure of the III-N system)—and GaN/InGaN/GaN heterojunctions in particular—can be used to dramatically increase tunneling currents (and thus TFET on-state currents). However, implementation of a GaN-based TFET required a low defect gate oxide/GaN interface. This has been achieved using the two-step wet-dry surface passivation.

A platform for benchmarking tunnel field-effect transistors (TFETs) for analog applications is presented and used to compare selected TFETs to FinfET technology at the 14-nm node. This benchmarking is enabled by the development of a universal TFET SPICE model and a parameter extraction procedure based on data from physics-based device simulators. Analog figures of merit are computed versus current density to compare TFETs with CMOS for low-power analog applications to reveal promising directions for the system development. To illustrate the design space enabled by TFETs featuring sub-60-mV/decade subthreshold swing, two example circuits including a picopower common-source amplifier and an ultralow-voltage ring oscillator are demonstrated.

Wrap-around gate GaN nanowire MOSFETs using Al2O3 as gate oxide have been experimentally demonstrated. The fabricated devices exhibit a minimum subthreshold slope of 60 mV/dec, an average subthreshold slope of 68 mV/dec over three decades of drain current, drain-induced barrier lowering of 27 mV/V, an on-current of 42 μA/μm (normalized by nanowire circumference), on/off ratio over 108, an intrinsic transconductance of 27.8 μS/μm, for a switching efficiency figure of merit, Q=gm/SS of 0.41 μS/μm-dec/mV. These performance metrics make GaN nanowire MOSFETs a promising candidate for emerging low-power applications such as sensors and RF for the internet of things.

Future generations of ultra-scaled logic may require alternative device technologies to transcend the limitations of Si CMOS; in particular, power dissipation constraints in aggressively-scaled, highly-integrated systems make device concepts capable of achieving switching slopes (SS) steeper than 60 mV/decade especially attractive. Tunneling field effect transistors (TFETs) are one such device technology alternative. While a great deal of research into TFETs based on Si, Ge, and narrow band gap III-Vs has been reported, these approaches each face significant challenges. An alternative approach based on the use of III-N wide band gap semiconductors in conjunction with polarization engineering offers potential advantages in terms of drain current density and switching slope. In this talk, the prospects for III-N based TFETs for logic will be discussed, including both simulation projections as well as experimental progress.

A tunnel field-effect transistor (TFET)-based pixel circuit for well capacity adjustment that does not require subthreshold operation on the part of the reset transistor is presented. In CMOS, this subthreshold operation leads to temporal noise, distortion and fixed pattern noise, becoming a primary limiting performance factor. In the proposed circuit, the asymmetric conduction associated with TFETs is exploited. This property, arising from the inherent physical structure of the device, provides the selective well adjustments during photo-integration which are demanded for achieving high dynamic range. A GaN-based heterojunction TFET has been designed according to the specific requirements for this application.

Owing to the unprecedented development in terahertz (THz) sources and detectors in the last decade, technologists and researchers have intensified their efforts to develop advanced THz sensing and imaging systems with superior performance and unique functionalities. One of the key elements to realize such systems is the ability to monolithically integrate high-performance semiconductor devices with THz antennas and other passive structures. In recent years, devices based on interband tunneling in III-V heterostructures have emerged as promising candidates for THz detection that offer extremely high nonlinearity, high sensitivity, low noise, fast response, and room temperature operation. In this paper, we first review the development of heterostructure backward tunnel diodes (HBDs) in the InAs/AlSb/AlGaSb material system that have been demonstrated with detection sensitivity that outperforms the current state of the art (e.g., the fundamental limit of Schottky diodes) and with noise-equivalent power (NEP) below 0.2 pW/Hz½. We then present the monolithic integration of HBDs with planar folded dipole antennas (FDAs) using submicrometer-scale airbridges to achieve optimized impedance matching for high-performance and compact THz detectors and focal-plane array (FPA) imaging systems. In addition, the potential of using HBDs for realizing THz systems with advanced functionalities such as spectroscopic FPAs (using frequency-tunable THz antennas) and polariametric detection/imaging systems will be discussed. Finally, the integration of HBDs into waveguides for more advanced THz sensing and imaging (e.g., a six-port reflectometer for near-field imaging) will be discussed.

In this study, the growth of high quality N-polar InGaN films by metalorganic chemical vapor deposition is presented with a focus on growth process optimization for high indium compositions and the structural and tunneling properties of such films. Uniform InGaN/GaN multiple quantum well stacks with indium compositions up to 0.46 were grown with local compositional analysis performed by energy-dispersive X-ray spectroscopy within a scanning transmission electron microscope. Bright room-temperature photoluminescence up to 600 nm was observed for films with indium compositions up to 0.35. To study the tunneling behavior of the InGaN layers, N-polar GaN/In0.35Ga0.65N/GaN tunnel diodes were fabricated which reached a maximum current density of 1.7 kA/cm2 at 5 V reverse bias. Temperature-dependent measurements are presented and confirm tunneling behavior under reverse bias.

The performance of In0.53Ga0.47As/GaAs0.5Sb0.5 quantum-well tunnel field-effect transistors (TFETs) for microwave-frequency detection is explored experimentally. The strong nonlinearity of the TFET transfer characteristic, which arises from a combination of band-to-band tunnelling between source and channel and gate modulation of the tunnel junction, can be utilised for high-sensitivity microwave detection. Using an analytical model, it is shown that TFET detection current sensitivity is approximately proportional to the second-order derivative of the transfer current-voltage characteristic. Though unoptimised, the large-area TFET detectors evaluated experimentally exhibit an unmatched voltage sensitivity of 112 kV/W, an impedance-matched noise equivalent power of 7.0 pW/Hz(0.5), and a bandwidth of 4 GHz. The microwave detection performance of TFETs can be enhanced by mitigating parasitic effects, improving the semiconductor/oxide interface quality, and scaling the gate area.

Future ultra-scaled logic and low-power systems require fundamental advances in semiconductor device technology. Due to power constraints, device concepts capable of achieving switching slopes (SS) steeper than 60 mV/decade are essential if scaling of conventional computational architectures is to continue. Likewise, ultra low power systems also benefit from devices capable of maintaining performance under low-voltage operation. Towards this end, tunneling field effect transistors (TFETs) are one promising alternative. While much work has been devoted to realizing TFETs in Si, Ge, and narrow-gap III-V materials, the use of III-N heterostructures and the exploitation of polarization engineering offers some unique opportunities. From physics-based simulations, performance of GaN/InGaN/GaN heterostructure TFETs appear capable of delivering average SS approaching 20 mV/decade over 4 decades of drain current, and on-current densities exceeding 100 μA/μm in aggressively scaled nanowire configurations. Experimental progress towards realizing III-N based TFETs includes demonstration of GaN/InGaN/GaN backward tunnel diodes by both MOCVD and MBE, and nanowires grown selectively by MBE and used as the basis for device fabrication.

Sensing and imaging at millimeter-wave and THz frequencies is promising for a wide range of applications, including security, industrial control, healthcare, and scientific metrology. The development of high-sensitivity, low noise detectors based on interband tunneling in III-V heterostructure devices, and their integration into subsystems is promising for realizing the potential of these applications. This paper describes recent work on both heterostructure backward diodes and tunneling field-effect transistors as sensitive detectors in the microwave through THz frequency ranges, as well as their integration into tunable pixel elements and focal plane arrays for imaging and sensing applications.

The device concept and simulated characteristics of III-nitride nanowire tunneling field-effect transistors (NW TFETs) are presented. These devices employ polarization engineering in GaN/InN/GaN heterojunctions to achieve appreciable interband tunneling current densities, combined with a nanowire cylindrical gate-all-around geometry to achieve a high degree of gate electrostatic control. Simulations indicate that III-nitride nanowire TFETs can be expected to achieve on-off current ratios of 10(11), I-OFF of 10(-10) mu A mu m(-1), sub-threshold slopes as low as 25 mV dec(-1) over 4 decades of current, and an I-ON of 50 mu A mu m(-1) at a supply voltage of 0.5 V. A parametric evaluation of the geometry dependence of the device performance is performed, and the optimal device design parameter ranges for III-nitride NW TFETs are identified. (C) 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim

An analytical compact model for tunnel field-effect transistor (TFET) circuit simulation is extended by adding a gate tunnel current model, a charge-based capacitor model, and a noise model. The equation set is broadly applicable across materials systems and TFET geometries and is readily fitted to rigorous physics-based device simulations and experimental results. To validate the gate current and charge models, technology computer-aided design (TCAD) simulations of a GaN/InN/GaN TFET are used. TCAD simulations show that the gate tunneling current depends on the gate-drain bias with a 100%/0% drain/source current partition. Terminal capacitances evaluated from the charge model agree well with simulations. The model is implemented in Verilog-A and the significance of gate current in the circuit design is illustrated in an amplifier design.

Devices based on GaN and related III-N materials are increasingly well established in RF power applications, and are under active research and development for power conversion and control applications. However, the unique material properties of the III-Ns make them a promising basis for applications well beyond these traditional applications. Novel device concepts that harness these material properties in conjunction with unconventional operational physics are being explored to serve needs in applications as diverse as millimeter-wave and THz electronics and sensing, low-power systems, and ultra-scaled low-power logic. Devices exploiting interband tunneling in III-N heterostructures for low-power logic, as well as impact ionization and plasma-wave propagation in GaN 2DEGs for millimeter-wave and THz sensing and electronics are under active investigation to provide new levels of performance.

By the insertion of thin InxGa1−xN layers into Nitrogen-polar GaN p-n junctions, polarization-induced Zener tunnel junctions are studied. The reverse-bias interband Zener tunneling current is found to be weakly temperature dependent, as opposed to the strongly temperature-dependent forward bias current. This indicates tunneling as the primary reverse-bias current transport mechanism. The Indium composition in the InGaN layer is systematically varied to demonstrate the increase in the interband tunneling current. Comparing the experimentally measured tunneling currents to a model helps identify the specific challenges in potentially taking such junctions towards nitride-based polarization-induced tunneling field-effect transistors.

The concept and simulated device characteristics of tunneling field-effect transistors (TFETs) based on III-nitride heterojunctions are presented for the first time. Through polarization engineering, interband tunneling can become significant in III-nitride heterojunctions, leading to the potential for a viable TFET technology. Two prototype device designs, inline and sidewall-gated TFETs, are discussed. Polarization-assisted p-type doping is used in the source region to mitigate the effect of the deep Mg acceptor level in p-type GaN. Simulations indicate that TFETs based on III-nitride heterojunctions can be expected to achieve ON/OFF ratios of 106 or more, with switching slopes well below 60 mV/decade, ON-current densities approaching 100 μA/μm, and energy delay products as low as 67 aJ-ps/μm.

This paper explores, for the first time, the use of high responsivity heterostructure backward tunnel diodes to enhance the conversion efficiency of ambient microwave power harvesters. Progress in advancing the performance of low power rectifiers has been slowed because the maximum possible efficiency using Schottky diodes has been reached. Measurements of RF-to-DC conversion efficiency at -40dBmJ2.4GHz are reported in this paper, showing that the backward diode outperforms the HSMS-285B Schottky diode by a factor of 10.5 and the Skyworks SMS 7630 by a factor of 5.5. A narrowband rectifier circuit was designed, fabricated and tested, showing a total efficiency of 3.8% for a 100nW input RF power and 18.2% at IIlW input RF power, at 2.35GHz.