The outsourcing of integrated circuit (IC) fabrication services to overseas manufacturing foundry has raised security and privacy concerns with regard to intellectual property (IP) protection as well as the integrity maintenance of the fabricated chips. One way to protect ICs from malicious attacks is to encrypt and obfuscate the IP design by incorporating additional key gates, namely logic encryption or logic locking. The state-of-the-art logic encryption techniques certainly incur considerable performance overhead upon the genuine IP design. The focus of this paper is to leverage the unique property of emerging transistor technology on reducing the performance overhead as well as preserving the robustness of logic locking technique. We design the polymorphic logic gate using silicon nanowire field effect transistors (SiNW FETs) to replace the conventional Exclusive-OR (XOR)-based logic cone. We then evaluate the proposed technique based on security metric and performance overhead.

This chapter considers one of the emerging technologies: silicon NanoWire (SiNW) field-effect transistors (FETs), and makes the following contributions. It introduces SiNW FET-based camouflaging layout and polymorphic gates to help obfuscate layouts and netlists. SiNW FETs, or more precisely the polarity-controllable feature, provide an ideal candidate for camouflaging gates since all these gates share the same structure with only four SiNW FETs used. The characteristics of SiNW FETs prove to us that this new device is not a drop-in alternative to traditional MOSFETs. However, the polarity-controllable SiNW FETs, with their unique property, can help build camouflaging gates without using extra FETs. The polarity control gate does not reduce the number of transistors required to implement NAND and NOR using SiNW FET technology. To further reduce the surcharge, instead of incorporating more logic gates for logic locking, our approach is to replace some portions of the original netlist with SiNW FET-based polymorphic logic gates.

Due to the outsourcing of chip manufacturing, countermeasures against Integrated Circuit (IC) piracy, reverse engineering, IC overbuilding and hardware Trojans (HTs) become a hot research topic. To protect an IC from these attacks, logic encryption techniques have been considered as a low-cost defense mechanism. In this paper, our proposal is to insert the multiplexer (MUX) with two cases: (i) we randomly insert MUXs equal to half of the output bit number (half MUX insertions); and (ii) we insert MUXs equal to the number of output bits (full MUX insertions). Hamming distance is adopted as a security evaluation. We also measure the delay, power and area overheads with the proposed technique.

We consider how the I-V characteristics of emerging transistors (particularly those sponsored by STARnet) might be employed to enhance hardware security. An emphasis of this work is to move beyond hardware implementations of physically unclonable functions (PUFs) and random number generators (RNGs). We highlight how new devices (i) may enable more sophisticated logic obfuscation for IP protection, (ii) could help to prevent fault injection attacks, (iii) prevent differential power analysis in lightweight cryptographic systems, etc.

Emerging devices have been designed and fabricated to extend Moore's Law. While the benefits over traditional metrics such as power, energy, delay, and area certainly apply to emerging device technologies, new devices may offer additional benefits in addition to improvements in the aforementioned metrics. In this sense, we consider how new transistor technologies could also have a positive impact on hardware security. More specifically, we consider how tunneling FETs (TFET) and silicon nanowire FETs (SiNW FETs) could offer superior protection to integrated circuits and embedded systems that are subject to hardware-level attacks - e.g., differential power analysis (DPA). Experimental results on SiNW FET and TFET CML gates are presented. In addition, simulation results of utilizing TFET CML on a light-weight cryptographic circuit, KATAN32, show that TFET-based current mode logic (CML) can both improve DPA resilience and preserve low power consumption in the target design. Compared to the CMOS-based CML designs, the TFET CML circuit consumes 15 times less power while achieving a similar level of DPA resistance.

Hardware security concerns such as intellectual property (IP) piracy and hardware Trojans have triggered research into circuit protection and malicious logic detection from various design perspectives. In this article, emerging technologies are investigated by leveraging their unique properties for applications in the hardware security domain. Security, for the first time, will be treated as one design metric for emerging nano-architecture. Five example circuit structures including camouflaging gates, polymorphic gates, current/voltage-based circuit protectors, and current-based XOR logic are designed to show the high efficiency of silicon nanowire FETs and graphene SymFET in applications such as circuit protection and IP piracy prevention. Simulation results indicate that highly efficient and secure circuit structures can be achieved via the use of non-CMOS devices.

Emerging devices have been designed and fabricated to extend Moore's Law. While traditional metrics such as power, energy, delay, and area certainly apply to emerging device technologies, new devices may offer additional benefits in addition to improvements in the aforementioned metrics. In this sense, we consider how new transistor technologies could also have a positive impact on hardware security. More specifically, we consider how tunnel transistors (TFETs) could offer superior protection to integrated circuits and embedded systems that are subjected to hardware-level attacks - e.g., differential power analysis (DPA). Experimental results on a light-weight cryptographic circuit, KATAN32, show that TFET-based current mode logic (CML) can both improve DPA resilience and preserve low power consumption in the target design. Compared to the CMOS-based CML designs, the TFET CML circuit consumes 15 times less power while achieving a similar level of DPA resistance.

With the globalization of the integrated circuit (IC) design flow of chip fabrication, intellectual property (IP) piracy is becoming the main security threat. While most of the protection methods are dedicated for digital circuits, we are trying to protect radio-frequency (RF) designs. For the first time, we applied the split manufacturing method in RF circuit protection. Three different implementation cases are introduced for security and design overhead tradeoffs, i.e., the removal of the top metal layer, the removal of the top two metal layers and the design obfuscation dedicated to RF circuits. We also developed a quantitative security evaluation method to measure the protection level of RF designs under split manufacturing. Finally, a simple Class AB power amplifier and a more sophisticated Class E power amplifier are used for the demonstration through which we prove that: (1) the removal of top metal layer or the top two metal layers can provide high-level protection for RF circuits with a lower request to domestic foundries; (2) the design obfuscation method provides the highest level of circuit protection, though at the cost of design overhead; and (3) split manufacturing may be more suitable for RF designs than for digital circuits, and it can effectively reduce IP piracy in untrusted off-shore foundries.

Source degeneration of access devices in the parallel (P)_ anti-parallel (AP) switching in Spin Transfer Torque Magnetic Random Access Memories (STT-MRAM) has ultimately been a limiting factor in the operational speed of these types of memories. In this work, new architectures for memory single-cells and arrays of cells are presented that utilize Schottky-Barrier Silicon Nanowire Field Effect Transistors with polarity control capabilities (e.g., SiNW-FETs), to substantially increase the performance of STT-MRAM, specifically Multi-Level Cell (MLC) STT-MRAM. The proposed design offers built-in reliability improvement as it omits one of the available four states in the MLC STT-MRAM memory facilitating the resistance level detection for peripheral circuitry. Our simulation results of the developed memory cell show 49.7% reductions in P-AP switching time, as well as 51.3% increases in available drive current under 1.4V supply voltage when compared to FinFET 22imi technology. With respect to memory arrays, the proposed architecture demonstrates an average write latency reduction of 37% in comparison with FinFET 22nm technology node.

With the globalization of integrated circuit (IC) design flow and the outsourcing of chip fabrication service, intellectual property (IP) piracy and malicious logic insertion become main security threats to tamper hardware infrastructures. While most of the protection methods are dedicated for digital circuits, we try to protect radio-frequency (RF) designs which are more likely to be IP piracy victims. For the first time, we apply the split manufacturing method in RF circuit protection. Three different implementation cases are introduced for security and design overhead tradeoffs, i.e., the removal of the top metal layer, the removal of the top two metal layers, and the design obfuscation dedicated for RF circuits. We also develop a quantitative security evaluation method to measure the protection level of RF designs under split manufacturing. Finally, a class-AB power amplifier is used for demonstration through which we prove that: 1) the removal of top metal layer or top two metal layers can provide high-level protection for RF circuits with lower request to the domestic foundries; 2) design obfuscation method provides highest level of circuit protection, though at the cost of design overhead; 3) split manufacturing is more suitable to RF designs than to the digital circuits and it can effectively improve hardware tamper resistance and reduce IP piracy in the untrusted off-shore foundries. Keywords-Hardware Tamper Resistance, Hardware Trust, IP Piracy, Power Amplifier, RF Circuits, Split Manufacturing

The hot carrier injection stress effect on a 65 nm low-noise amplifier at the 70 GHz range of operation has been studied. The experimental data show that the minimum noise figure increases ( ~2 dB) and the maximum small-signal power gain decreases (~3 dB) after 10 h of HCI overstress due to transconductance degradation as evidenced by 65 nm individual transistor measurement.

Hardware security concerns such as IP piracy and hardware Trojans have triggered research into circuit protection and malicious logic detection from various design perspectives. In this paper, emerging technologies are investigated by leveraging their unique properties for applications in the hardware security domain. Three example circuit structures including camouflaging gates, polymorphic gates and power regulators are designed to prove the high efficiency of silicon nanowire FETs and graphene Sym FET in applications such as circuit protection and IP piracy prevention. Simulation results indicate that highly efficient and secure circuit structures can be achieved via the use of emerging technologies.

Process and temperature invariant voltage multiplier performance has been examined. The analytical predictions of ripple voltage and frequency response are in good agreement with ADS simulation results. In addition, a threshold voltage compensation scheme is investigated to improve the output voltage sensitivity against process variations and temperature fluctuation. The threshold voltage compensation technique effectively reduces the temperature and process variability on the voltage multiplier performance. (C) 2014 Elsevier Ltd. All rights reserved.