GlobalFoundries (also known as GF) is an American semiconductor foundry headquartered in Santa Clara, California, United States. GlobalFoundries was created by the divestiture of the manufacturing arm of Advanced Micro Devices (AMD). The Emirate of Abu Dhabi is the owner of the company through its subsidiary Advanced Technology Investment Company (ATIC). The firm manufactures integrated circuits in high volume mostly for semiconductor companies such as AMD, Broadcom, Qualcomm, and STMicroelectronics. It has five 200 mm wafer fabrication plants in Singapore, one 300 mm plant each in Germany and Singapore, and three plants in the United States: one 200 mm plant in Vermont (where it is the largest private employer) and two 300 mm plants in New York.GlobalFoundries plans to become a publicly traded company in 2022.
In this work, we propose a novel differential photonic static random access memory (pSRAM) bitcell design using fabrication-friendly photonic components. The proposed pSRAM overcomes the key limitations of traditional electrical SRAMs, which struggle with speed and power efficiency due to increasing bitline/wordline capacitance and interconnect resistance associated with long electrical wires as technology scales. By utilizing cross-coupled micro-ring resonators and differential photodiode structures, along with optical waveguides instead of traditional wordlines and bitlines, our pSRAM exhibits high-speed, and energy-efficient performance. The pSRAM bitcell demonstrates a read/write speed of 40 GHz, with a switching (static) energy consumption of approximately 0.6 pJ (0.03 pJ) per bit and a footprint of 330x290 um^2 using the GlobalFoundries 45SPCLO process node. These bitcells can be arranged into a 2D memory array, enabling large-scale, on-chip photonic memory subsystems ideal for high-speed memory, data processing and computing applications.
Time-domain nonvolatile in-memory computing (TD-nvIMC) offers a promising pathway to reduce data movement and improve energy efficiency by encoding computation in delay rather than voltage or current. This work presents a fully integrated and reconfigurable TD-nvIMC macro, fabricated in 28 nm CMOS, that combines a ferroelectric FET (FeFET)-based content-addressable memory array, a cascaded delay element chain, and a time-to-digital converter. The architecture supports binary multiply-and-accumulate (MAC) operations using XORand AND-based matching, as well as in-memory Boolean logic and arithmetic functions. Sub-nanosecond MAC resolution is achieved through experimentally demonstrated 550 ps delay steps, representing a 2000 & times; improvement over prior FeFET TD-nvIMC work, enabled by multilevel-state calibration with <= 100 ps resolution. Write-disturb resilience is ensured via isolated triple-well bulks. The proposed macro achieves a measured throughput of 222.2 MOPS/cell and energy efficiency of 1887 TOPS/W at 0.85 V, establishing a viable path toward scalable, energy-efficient TD-nvIMC accelerators.
Understanding and monitoring phase transformations in tungsten thin films is crucial for advancing applications in spintronics, including MRAM technology. This study investigates spectroscopic ellipsometry as a non-destructive method for identifying and distinguishing between the tungsten phases beta-tungsten ( β -W) and alpha-tungsten (α-W) in thin films. In this study, β -W thin films of, ranging from 15 to 150 nm in thickness, were deposited on silicon substrates using DC magnetron sputtering. Phase transition to α-W was then induced in selected samples. The films were characterized using atomic force microscopy (AFM), scanning electron microscopy (SEM), grazing-incidence x-ray diffraction (GIXRD), x-ray reflectivity (XRR), and four-point probe resistivity. Optical properties were subsequently measured using a spectroscopic ellipsometer, and the data were used to build and fit B-Spline models in CompleteEASE 6 software. The optical parameter data from the tested samples were then fitted successfully for both tungsten phases. The data analysis has shown distinct refractive index patterns for the α -W and β -W phases in films with thicknesses of 15, 30, and 60 nm. This work demonstrates that spectroscopic ellipsometry can effectively be used as an additional in situ tool, complementing other characterization techniques, to detect and monitor phase transformations in tungsten thin films.
Ferroelectric field-effect transistors (FeFETs) are strong candidates for synaptic devices in neuromorphic and in-memory computing due to their multi-level programmability, non-volatility, and complementary metal-oxide-semiconductor (CMOS) compatibility. In this work, we experimentally demonstrate multi-bit operation of FeFET synapses integrated on GlobalFoundries’ 28nm CMOS process. Specifically, the work uses an incremental pulsing scheme, showing stable access to intermediate polarization states and long-term retention. We further examine the role of device size, read-out gate voltage, and array topology as fundamental design trade-offs, showing that larger-area FeFETs provide more deterministic state programming, while smaller devices favor integration density. Finally, we compare 1-FeFET and nT–1FeFET array architectures with static random-access memory (SRAM), outlining the density, selection, and scalability implications of each. These findings provide both device-level insights and circuit-architecture considerations, guiding the co-design of FeFET-based synaptic arrays for future neuromorphic accelerators.
This paper describes the design and measurement of a low-power 5.5 GHz LNA with an on-chip biasing circuit for Wi-Fi,6/6E applications. The LNA parameters may vary from wafer/site to wafer/site when they are biased externally or on-chip voltage references. The cascode current mirror is embedded to generate on-chip bias for common-source (CS) and common-gate (CG) devices. The on-chip biasing circuit reduces the wafer to wafer deviation of the biasing point which improves the stability and consistency of LNA performance. The LNA is designed using floating body FET for CS device and body contacted FET for CG device. The noise figure of LNA is improved by optimizing the gate inductor with tapered dual thick copper metals. The prototype is fabricated and measured on a high resistivity SOI process with 65 nm gate length. The measurements are performed across different wafers and sites to validate the importance of on-chip biasing for LNA. The measurements show that the gain is 19.7 dB, noise figure of 0.64 dB and IIP_3 of −1.8 dBm while consuming 6.6 mA from a 1.6 V supply. More importantly, wafer to wafer variation of LNA gain and current is only 0.025 dB and 0.39 mA respectively.
