Post-quantum cryptographic (PQC) algorithms are being standardized to prepare for the quantum computing era. CRYSTALS-Kyber is the chosen PQC scheme for Public Key Encryption. Number Theoretic Transforms (NTT) and SHA-3 core are the key primitives used in CRYSTALS-Kyber. Hence, fast and efficient implementations of these primitives are important. Typically, rapid prototyping of hardware blocks is done using tools like Vivado HLS. However, HLS tools don’t always produce optimal results and the generated RTL code is not portable across platforms. This paper implements NTT and SHA-3 cores using a Python-based DSL to generate synchronous digital circuits, which perform better than Vivado HLS. The tool is lightweight and easy to use and the generated RTL is portable for any FPGA or ASIC flows. Moreover, due to the availability of the PYNQ-Z2 framework, FPGA-based testing can be done using Python, enabling Python-only hardware-software flow.
In the realm of medical imaging, identifying and classifying tumors using light weight machine learning algorithms require edge detection procedure. This renders the process of edge detection as a task of utmost importance which makes a difference between a right and wrong diagnosis. Due to its emergent nature , prompt and accurate diagnosis necessitates parallel and real-time processing. The process is made easier by the reconfigurable and parallel processing capabilities of field programmable gate array (FPGA). This paper presents the design and implementation of a custom Intellectual Property (IP) core for processing edge detection algorithm on FPGA. The proposed IP core is made to effectively use FPGA hardware acceleration to compute the edges of brain tumors. The scalable design of the core makes it simple to incorporate it into a range of FPGA-based systems and applications. The design of such custom IP core is achieved with the help of high level synthesis (HLS) which is then integrated and implemented on PYNQ Z2 board. The core is synthesized and tested to determine the performance metrics such as throughput, resource utilization, and power consumption. Effectiveness of the proposed IP core is demonstrated by experimental results. This IP core is designed in such a way that it processes the image and offers an adaptable and effective edge detection solution. This in turn opens the doors for integration into a range of FPGA-based real time applications and systems in various domain such as industrial automation, robotic surgery, and autonomous vehicles.
The increasing prevalence of radiation-sensitive applications in modern electronic devices has made it critical to understand the impact of ionizing radiation on device performance and reliability. FinFETs, due to their unique three-dimensional structure, present a particular challenge in this regard. In this manuscript, we perform heavy ion irradiation analysis on FinFETs to investigate the effects of ionizing radiation. Our results show that the heavy ion radiation can significantly impact the device performance and that the impact is highly dependent on by hitting the heavy ion at multiple locations, varied inclined angles, and different track radius. The outcomes revealed that the device is more susceptible to radiation at drain/channel interface junction compared to all the other locations. Moreover, when reducing the heavy ion strike angle inclination from 60 degrees-10 degrees, the charge collected by drain increased rapidly by an amount of 43.1% making the FinFET more vulnerable to radiation. Further, by increasing the ion track radius from 5 nm to 20 nm, made the FinFET sensitive to heavy ion strike by noticing an increase in charge collection by 39.4%. Our findings highlighted the need for careful design considerations and the more sensitive areas in the development of FinFETs for radiation-sensitive applications.
The Number Theoretic Transform (NTT) is a mathematical concept that solves complex problems in cryptography. It is recognized as a very efficient transform for the multiplication of two polynomials with high degrees, which have integer coefficients. It is widely used in practical implementations of cryptography schemes that are lattice-based. The NTT can be considered a variant of the Discrete Fourier Transform (DFT) that operates on integers. It deals with a ring of integers with the modulus of a prime number. The transform involves arithmetic in a modular approach, making it suitable for computations in a finite field. However, solutions implementing the NTT suffer from computational inefficiencies, limiting applications in various critical domains such as cryptography, signal processing, and arithmetic operations in finite fields. There is a need for an optimized hardware solution for the computation of the NTT in VLSI design. There are limitations on the modulus to be in a particular form. To address this gap, this work aims to design, validate, and characterize an Intellectual Property (IP) Core based on the NTT, catering to the need for specialized hardware that facilitates integration into diverse VLSI designs. The work has been carried out on the ARTY Artix-7 100T FPGA Development board with part number XC7A100TCSG324-1 with multiple inputs of different dimensions. RTL implementation of the Number Theoretic Transform has been done to verify the accuracy of the computation. Once it is found to be accurate, an IP core has been developed that meets the timing and power constraints. The performance metrics have been calculated for the characterization of the NTT IP core. The work has been carried out with two models of different dimensions. On-chip debugging with the FPGA is done on the created models to validate the NTT computations of given input sequences. It is observed that there are no limitations in the modulus or the twiddle factor for this design. Additionally, this design accounts for computational accuracy on the given inputs within the specified data limits.
Edge detection techniques play a major role in image segmentation which is one of the pre-processing steps in the image or video processing pipeline. These methods remove superfluous information while preserving important pixels. They are capable of detecting the change in brightness in digital images to identify borders/edges. It is an acknowledged fact that the Canny edge algorithm performs better than the other edge-detecting techniques. However, some processes are complex, and others are susceptible to noise. Before applying the edge detection to the images, in this study, the Canny edge detection is improvised utilizing histogram equalization techniques like CLAHE and noise-removal with bilateral/gaussian filtering. This method made use of OpenCV libraries and was implemented in a Jupyter notebook with Python. Experimental results show that the improved algorithms are more flexible in recognizing more edge features, more noise-resistant, and capable of differentiating targets from the background. The Zynq Ultrascale+ MPSoC is utilized in the hardware implementation of the suggested techniques. Since the Programmable Logic (PL) portion of the board can handle more sophisticated computations in high-speed applications, the Programming System (PS) portion of the board is used for implementation. When compared to previous relevant papers and simple, sophisticated techniques, the approaches provide a good performance.
This paper presents an automated framework for analog/mixed-circuit synthesis using a Multi-Objective Optimization-driven Genetic Algorithm (MOO-GA). The proposed methodology employs adaptive non-dominated sorting genetic algorithm to efficiently explore the design space and identify the optimal configuration of circuit parameters, including transistor geometries (W/L), bias currents, DC input voltages, and compensation capacitance. This approach aims to achieve desired performance metrics within a two-stage CMOS operational amplifier. Python serves as the development platform for the adaptive MOO-GA, while Cadence Virtuoso Spectre validates the generated designs within the constraints of standard UMC 180 (nm) CMOS technology. Six key performance metrics, encompassing area, power dissipation, open-loop DC gain, slew rate, unity gain-bandwidth, and phase margin guide the optimization process, shaping the Pareto frontier. The adaptive mechanism incorporated in the MOO-GA demonstrably enhances the diversity and robustness of the achieved Pareto optimal solutions. Comprehensive simulation results confirm the efficacy and feasibility of the proposed algorithm, paving the way for efficient and automated design of high-performance analog/mixed circuits.
Memristor, also known as Resistive Random Access Memory (ReRAM), enables in-memory computing by processing data directly within storage locations, thus mitigating the data transfer bottleneck between the processor and memory in high-speed applications. However, existing methods for implementing addition of two n-bit operands within ReRAM/memristor crossbar structures do not ensure minimal device utilization or minimal ReRAM/memristor read-write cycles. In this paper, we propose a novel approach for implementing n-bit addition in ReRAM crossbars to optimize the usage of the ReRAM device and minimize read-write cycles. We develop the ReRAM Sequence Graph (ReSG) to efficiently represent adder functionality and systematically allocate ReRAM devices to ReSG nodes. Furthermore, we present a scheduling mechanism for implementing ReSG nodes within ReRAM crossbars, accelerating the execution of the addition operation. Experimental evaluations show that our method surpasses current approaches, achieving better device utilization and reduced read-write cycles.
Histogram is an important feature of the digital images used in many image transformations. This paper proposes an efficient VLSI architecture of histogram generation and equalization of the images with the range of pixel values from 0 to 255. In our proposed design, the delay is reduced as compared with various existing designs. We have eliminated the requirement of histogram storage unit. However, the temporal buffers are introduced in our proposed designs to store the histogram along with the pipelined divider unit. It lowers the critical path delay of the proposed design. All the existing and proposed architectures are implemented with 45 nm CMOS technology. The synthesis results reveal that, for the implementation of (22 x 23)-point grey image, the proposed architecture of histogram equalization lowers the delay by 83% and 85%, respectively, in comparison to the current designs as shown in [13] and [14].
This paper investigates the vulnerability of VLSI architecture to hardware trojans, with a specific focus on moving average filter-based digital signal processing (DSP) systems. A highly parameterized and scalable window-size moving average filter is designed. A novel hardware trojan architecture is proposed and injected into the design with minimal area overhead on Xilinx’s Zynq UltraScale+ MPSoC FPGA board. The malicious circuit will make the desired output noisy, decreasing the signal-to-noise ratio and thus hampering the circuit’s overall functionality at the register transfer level (RTL).
Approximate parallel prefix adders (AxPPA) are a type of circuit that can perform addition operations on binary numbers with high speed and low power consumption with less area. These circuits provide approximate results, which means that they sacrifice accuracy for efficiency. This trade off makes them ideal for use in applications where speed is more important than precision. In recent years, there has been a growing interest in the development of these circuits, as they have the potential to revolutionize the field of digital signal processing. In this paper, an overview of approximate parallel prefix adders and methods for reducing the error rate of AxPPA by modification of the architectures for the following PPA adders: approximate Knowles (AxKWPPA), and Sklansky (AxSKPPA). The proposed adders aim at reduce the area, delay and Power delay Product. These proposed adders designed, simulated and implemented with Verilog HDL (IEEE 1364-2005), Xilinx Vivado software tool (Xilinx Vivado2018.1) and Digilent Artix7 FPGA board (XC7A35TICSG324-1L) respectively. The proposed adders verified by implementing them in FPGA In the Loop for the image enhancement and contrast applications.
This work briefs the stacked dynamic comparator (SDC) for analog mixed-signal applications. Four-clock switches make it work at high speed with reduced power. The input differential sensing action during pre-charge is performed, and the output voltage is independent of output node capacitance. The parasitic resistance is reduced, due to which the latch delay is also reduced. The stacked latch arrangement makes the leakage power dissipation negligible. The proposed SDC circuit exhibits offset voltage, dynamic power, leakage power, and delay that are 1.34x, 0.48x, 2.56x, and 1.64x, respectively, compared to conventional designs. These metrics indicate that the SDC circuit is highly suitable for high-performance sensing applications in ADC. All simulations have been handled by the Cadence virtuoso tool using an industry-standard UMC 65nm technology node.
Super-resolution refers to a class of techniques for producing high-resolution images from their low-resolution counterparts, using computational algorithms and methods. The higher the resolution, the greater the detail in the image, which is critical for current digital imaging applications. The techniques can either be classical or deep learning (DL) based methods like convolutional neural network (CNN). Although the CNN-based methods provide better results in terms of image reconstruction quality, the computational complexity due to the increasing number of parameters makes it difficult to provide real-time performance without the additional cost of resource utilization. In this paper, we propose optimizations to the fast super-resolution convolutional neural network (FSRCNN), a CNN-based super-resolution method by applying suitable quantization and modifications, for reducing the computational cost as well as memory footprint and implementing a hardware-efficient design on FPGA through FINN. In addition to achieving nearly a 50% reduction in resource utilization, our design enables real-time x2 image super-resolution from 1080p HD to 4K UHD with no significant loss in image quality compared to the original FSRCNN network.
This paper focuses on the proposal of a novel three-stage operational amplifier (Op-Amp) to meet the unique demands in Internet of Things (IoT) applications. The aim is to elevate essential performance parameters, notably including gain, slew rate, common-mode rejection ratio (CMRR), thereby affording a pronounced degree of precision and adaptability in the domain of signal processing. A three-stage Op-Amp topology has been proposed, incorporating techniques to enhance its gain, slew rate, and common-mode rejection ratio (CMRR). The novel topology has split length mosfets in the differential input stage and a pmos connected between Vdd and output node to enhance the performance of the three-stage Op-Amp. The design has been done for the GPDK 90 nm technology node. Extensive simulations have been conducted to validate the proposed three-stage Op-Amp’s operational correctness. Additionally, the Op-Amp’s performance has been thoroughly assessed through Process Voltage Temperature (PVT) analysis, and Monte Carlo mismatch analysis. This novel three-stage Op-Amp design promises to significantly improve signal processing capabilities and enhance the performance of systems relying on precision amplification.
Advancements in quantum circuit manufacturing methodologies have exhibited substantial progress over the past decade. One persisting challenge and technological constraint in this domain is the Nearest Neighbour (NN) implementation, necessitating physical qubits to be adjacent. One of the promising solutions to addressing this nearest neighbor problem was recognized, revealing that optimizing the grid selection could lead to a substantial reduction in the conversion cost for nearest neighbors and a more efficient utilization of SWAP operations. We have employed a mapping scheme to situate them effectively within suitable 2D grids. The conversion of quantum circuits into NN-compatible designs demonstrates promising outcomes, surpassing heuristic and meta- heuristic techniques. Through experimental evaluations and comparisons with state-of-the-art methodologies, we have identified significant enhancements. Experimental results exhibit notable breakthroughs, showcasing advancements of approximately 7.63%, 11.76%, 20.5%, 25.46% and 11.56% over existing 2D works. Furthermore, considerable improvements of 16.87% and 5.46% have been registered over large 2D benchmarks and meta-heuristic approaches, respectively.
The market for high-performance ICs (integrated circuits) and packages is rapidly expanding with 5G, automotive, IoT devices, aerospace, consumer electronics, and medical devices. MCM (Multi Chip Module)/SiP (System in Package) modules' content and complexity is increasing with multiple technologies for IC, filters, switches, and other components. Circuit design, layout design, and electromagnetic analysis are often performed using separate tools and by different design specialists. Disjointed tools pose significant challenge in IC design process to address the level of complexities and time-to-market constraints. This requires a shift from MCM/SiP to heterogeneous integration. While MCM/SiP Layout modules’ content is increasing, trace features are getting thinner and closer to one another with higher risk for coupling, thereby emphasizing the need for electromagnetic (EM) analysis to optimize the effects of physical layout on electrical design within same cockpit. We present a methodology for designing ICs and packages together using a RF Solution which directly addresses lack of traceability of design changes, and errors in information exchange across tools. It enhances overall design team productivity by global optimization and characterization of the design under development, optimizing for signal integrity, power integrity, thermal performance, and constraints.
This work investigates the effect of voltage and frequency variations on the hysteresis curve of the non-linear memristor model developed in the LTspice tool with different window functions namely Joglekar, Prodromakis, and Jinxiang. The methods to improve the hysteresis loop at higher frequency have been postulated. The usefulness of the memristor has been explored in the CMOS-based logic gates by replacing the bulk PMOS with a memristor to reduce their size and improve the performance without much compromising on parameters like delay and power consumption at different frequency ranges. In addition, the implementation of a hybrid CMOS-Memristor-based SRAM cell has been made and a comparative study on delay and noise margin analysis during both read and write operations concerning the traditional 6T CMOS-based SRAM cell has been carried out. The memristor modelling and circuit implementation have been carried out in the LTspice tool with TSMC 180nm technology node.
Recent years have seen significant advancements in artificial intelligence (AI) and machine learning (ML) algorithms. Over the years, several classification systems using ML have been developed for classifying various data. A significant number of mathematical operations are performed on the data during the classification processes. These procedures can take a long time to sequentially complete on a system’s primary processor, which might delay other pending tasks. In order to minimize processing time, these processes can also be performed in parallel. Field Programmable Gate Array (FPGA) devices can be utilized to construct parallel processing architectures tailored to classification applications. System on chips (SoC) have been introduced in recent years, which contain an FPGA chip, memory, external storage units, and various supporting peripherals. As a result, it is now very much easier to create a hardware-accelerated design with a parallel FPGA-based accelerator. In this research paper, we have designed a custom intellectual property (IP) core for concatenation of ten linear support vector machines (SVMs) to classify multi-class handwritten digits from the Modified National Institute of Standards and Technology (MNIST) handwritten digit dataset. This custom IP core will function as a hardware accelerator for the system to aid the inference process.
In SoC product development process, Digital IP signoff is an important step. Also sometimes time consuming. Some of the signoff guidelines are: (a)Perform logical synthesis (b)Perform Linting (c) Low power Analysis (d)ATPG goal check etc. In an industrial product development environment, there are lot of products (SoC) get developed concurrently in tight schedule. Also, the future roadmap shows surge in demand for SoC(s). We needed to develop a scalable, modern, data driven automation which not only should expedite the Digital IP signoff to Sub-System/SoC but also creates a standardized pluggable interface to apply different shift-left methodologies easily to improve the quality of the integration.
The increasing complexity of System-on-Chip (SoC) architectures requires efficient data transfer and integration of multiple processing units. Network-on-Chip (NoC) technology is essential for managing communication within Multi-Processor Systems-on-Chip (MPSoCs). Manual design of NoC frameworks is time-consuming, error-prone, and costly. This paper presents an automated framework for generating and configuring RISC-V based NoC-MPSoC topologies on FPGAs. By automating the creation of MxN mesh-based topologies (M is number of rows and N is number of columns), including routers, network interfaces (NIs), and processors, the proposed framework reduces manual intervention, accelerates the design process, and minimizes human errors. The framework’s adaptability and scalability are validated across various router sizes, confirming its effectiveness in optimizing resource usage and reducing costs. The automated design was implemented and verified using AMD Vivado, Integrated Logic Analyzer (ILA), and Virtual Input-Output (VIO) tools on a ZedBoard.
Accurate runtime prediction is crucial in VLSI physical design processes to enhance resource management, scheduling, and overall project efficiency. This paper presents a methodology for predicting runtimes of floorplanning, placement, and routing phases using machine learning models. A comprehensive dataset was generated from 433 different VLSI designs using Cadence Genus and Innovus. Various machine learning algorithms, including linear regression, decision trees, and advanced ensemble methods such as gradient boosting, were evaluated to identify the most effective model. The Gradient Boosting Regressor demonstrated superior performance, achieving high R 2 scores and low RMSE values. By integrating these models into the VLSI design workflow, we can achieve significant improvements in runtime prediction accuracy. This approach not only enhances the efficiency of the design process but also reduces overall design time and costs. The findings suggest that machine learning can play a pivotal role in optimizing VLSI design workflows, paving the way for faster and more cost-effective development of advanced electronic devices.
