Trusted Platform Modules (TPMs) are widely used in modern digital systems to provide a root-of-trust and support for various security applications. Highly trusted encryption algorithms play a crucial role in secure applications such as message authentication, digital signatures, pseudorandom number generation, and cryptographic key derivation. Dedicated hardware accelerators for hashing enhances the performance of cryptographic operations in TPMs. With the rise of open-source architectures like RISC-V, integrating cryptographic accelerators into TPMs is vital for secure embedded designs. In this context, this paper presents a high-performance, AXI-enabled SHA-3 hardware accelerator integrated into an indigenous RISC-V based TPM, named BHARAT-TPM. The proposed design explores the micro-architecture of the Keccak SHA-3 hash function and its sponge construction for efficient hash computation. The SHA-3 accelerator supports four output hash variants (224, 256, 384, and 512 bits), along with extendable-output functions (XoF), interfaces with the system via AXI-4 compatible control and data registers, ensuring seamless integration into RISC-V based TPM. The SHA-3 accelerator is implemented in Verilog RTL and verified against NIST test vectors at simulation level. Post Verification, the accelerator is integrated with the BHARAT-TPM is prototyped on Xilinx Virtex UltraScale VCU 118 FPGA devices and validated for TCG 2.0 hashing commands and hashing based application workloads. This paper presents an analysis of area utilization, maximum operating frequency, and throughput. The proposed SHA-3 accelerator achieves a peak throughput of 21.5 Gbps, demonstrating and suitability for high-speed cryptographic operations in TPM based security applications.
Accurate signal integrity analysis in high-frequency three-dimensional integrated circuits (3D-ICs) is critical, as crosstalk and noise coupling in dense Through-Glass Via (TGV) arrays can severely degrade performance. Conventional electromagnetic simulations provide accuracy but are computationally prohibitive for iterative design. To overcome this limitation, we introduce a Liquid Transformer model that learns temporal and spatial dependencies of crosstalk effects directly from data. A custom coaxial-TGV dataset with multiple signal-line configurations was constructed to capture realistic high-frequency behaviors. The model achieves strong predictive performance, with training and testing mean squared error (MSE) of 0.0102 and 0.0103, cosine similarity of 0.9301 and 0.9240, and Pearson correlation of 0.8484 and 0.7689, respectively. These results demonstrate the Liquid Transformer’s effectiveness in modeling complex signal dynamics while offering a faster, data-driven alternative to electromagnetic simulation for next-generation 3D-IC design.
This paper presents a novel Transformer (XFMR) design intended for integrated millimeter-wave (mmWave) applications. The XFMR consists of an 8-shaped primary inductor and a dumbbell-shaped secondary inductor. This structure addresses key challenges in on-chip XFMR design by improving electromagnetic interference (EMI) suppression, reducing unwanted signal coupling, and optimizing magnetic field symmetry. Additionally, the geometry enables better layout efficiency and isolation, contributing to improved performance in tightly integrated environments. To demonstrate the practical advantages of the proposed XFMR, it is implemented in a low-voltage, low-phase-noise (PN) LC VCO designed for 23.8–27.2 GHz operation. Simulation results in TSMC 65 nm CMOS technology show a tuning range of 3.4 GHz, a PN lesser than 110 dBc/Hz at 1 MHz offset, and a figure-of-merit (FoM) greater than 186 dBc/Hz, at 0.6 V supply. These results validate the effectiveness of the XFMR in enhancing VCO performance, highlighting its potential for use in high-performance mmWave design.
Recent progress in MEMS resonant-fin-transistors (RFT) has enabled very high-Q active mode resonators, promising crystal-less monolithic clock generation for Millimeter-wave (mmWave) systems. However, there is a strong need for the design of mmWave oscillators that utilize the high-Q of active-mode RFT (AM-RFT) optimally, while handling unique challenges such as resonator’s low electromechanical transduction. In this brief, we develop a theory and through design and post-layout simulations in the 14 nm Global Foundry (GF) process, we show the first active oscillator with AM-RFT at 30 GHz, which improves the fundamental limits of phase noise (PN) and figure-of-merit (FoM) when compared with the oscillators with conventional LC resonators. For AM-RFT with Q-factor of ∼ 10k, post-layout simulation results show that the proposed oscillator exhibits phase noise of less than -140 dBc/Hz and FoM greater than 228 dBc/Hz at a 1 MHz offset for a 30 GHz center frequency, which are 25 dB better than the existing monolithic LC oscillators.
In modern digital systems, the demand for low-power, high-performance arithmetic units is steadily increasing, particularly in embedded and portable applications. This work presents a comparative performance enhancement study of Carry Select Adders (CSLA) using FinFET-based Modified Gate Diffusion Input (MGDI) logic and Variable Bit Carry Look-Ahead (CLA) logic. The focus is on optimizing 4-bit, 8-bit, 16-bit, and 32-bit CSLA architectures to reduce power and delay while preserving area efficiency. This study evaluates the effect of logic-level enhancements and FinFET technology on conventional CSLA structures. FinFETs offer improved electrostatic control and reduced leakage, making them ideal for sub-nanometer designs. The MGDI logic further contributes to logic simplification and power savings. Simulation results show that the proposed FinFET-based MGDI CSLA achieves up to 46
