Soitec is a France-based international industrial company specialized in generating and manufacturing high performance semiconductor materials.Soitec's semiconductor materials are used to manufacture chips which equip smartphones, tablets, computers, IT servers, and data centres. Soitec's products are also found in electronic components used in cars, connected objects (Internet of Things), as well as industrial and medical equipment.Soitec's flagship product is silicon on insulator (SOI). Materials produced by Soitec come in the form of substrates (also called "wafers"). These are produced as ultra-thin disks that are 200 to 300 mm in diameter and are less than 1 mm thick. These wafers are then etched and cut to be used for microchips in electronics.
In this work, we demonstrated the fluorine (F) plasma-treated indium-tin-oxide field-effect transistors (ITO:F FETs) with channel lengths ranging from 40 nm to 10 & micro;m. Their electrical characteristics and dark-state positive-bias-temperature-instability (PBTI) behavior were systematically investigated over a broad temperature range from 77 to 375 K. Our results show that the fluorine plasma treatment effectively tunes the threshold voltage (V-TH) of indium-tin-oxide (ITO) field-effect transistors (FETs) while preserving strong drive current and normal switching behavior, consistent across devices with different channel lengths. Notably, the 40-nm ITO:F FET demonstrates excellent dark-state PBTI stability. After PBTI stressing up to 10 ks under an overdrive field (E-OX) of 2.5 MV/cm, the ITO:F FET exhibits threshold voltage shifts (Delta V-TH) of 42 mV at 300 K. These findings highlight the potential of fluorine plasma treatment to improve the electrical characteristics and PBTI stability of ITO FETs.
Two-tone large-signal Intermodulation Distortion (IMD) measurements are explored for the characterization of substrate nonlinearities, as it is envisaged to provide several advantages at high frequencies over the conventional single-tone large-signal Harmonic Distortion (HD) approach. However, this work demonstrates through analytical modeling, simulations, and measurements that the equivalence between the two approaches breaks down when memory-effects (such as carrier response lag due to their finite inertia) exist between the Device Under Test’s (DUT) nonlinear transfer coefficient and the input signal.
In this work, we experimentally demonstrated a back-end-of-line (BEOL)-compatible nonvolatile SRAM (NV-SRAM) leveraging HfO2-based metal/ferroelectric/metal (MFM) capacitors for nonvolatility and ITO-channel FETs for enhanced integration density. With a maximum process temperature of 400 degrees C, our NV-SRAM can be seamlessly integrated into BEOL, enabling monolithic 3-D vertical stacking of multilayer memories above silicon CMOS circuits for ultrahigh density and bandwidth. We successfully demonstrated store and recall operations in the fabricated NV-SRAM cell, which eliminates standby power consumption using FE capacitors and operates at a low VDD of 1.5V with a plate line (PL) voltage of 2 V. Experimental evaluations of the cell with indium-tin-oxide (ITO) FETs featuring a 75-nm channel length, along with SPICE simulations of ultrascaled cells, underscore the significant potential of BEOL NV-SRAM for data-centric computing.
The evolution of wireless communication systems toward 5G Advanced and Non-Terrestrial Networks is driving stringent requirements on radiofrequency (RF) front-end filters, which must offer high selectivity, low insertion loss, excellent linearity and minimal footprint. This paper presents the development of a flexible generation of RF Surface Acoustic Wave (SAW) filter architecture designed to address these emerging challenges. Leveraging advanced substrate engineering, with the POI stacks, the proposed new electro-elastic filter architecture achieves enhanced frequency performances while ensuring scalability for multiple frequencies, bandwidth and standard integration. The approach paves the way for high-performance SAW filtering solutions suitable for future RF system-on-chip and module-level integration, enabling compact and cost-efficient designs for upcoming mobile, navigation and satellite platforms.
In this letter, we present a room temperature fluorination (RTF) treatment that offers a low-cost, back-end-of-line (BEOL)-compatible route to threshold voltage (VTH) engineering in oxide semiconductor (OS) FETs. Under the optimized condition, a 100 nm channel length ITO:F FET exhibits near-zero VTH, nearly hysteresis-free operation, and a subthreshold swing (SS) of 68 mV/dec. AFM measurements indicate no obvious plasma-induced roughening after RTF, while XPS confirms fluorine incorporation after the treatment. Selective application of RTF enables a BEOL-compatible inverter with a record-high DC voltage gain of 2687 V/V at VDD = 4 V. A unipolar inverter composed of 200 nm channel length (LCH) FETs further achieves a static noise margin (SNM) of 0.41 V at VDD = 1 V. These results highlight RTF as a practical path toward scalable, low-voltage oxide logic for monolithic 3D integration.
