In this paper, we propose ORCA, an oracle-less, CNN-based structural attack methodology that circumvents logic locking by predicting the key of a locked gate-level netlist and reversing it to RTL. The proposed methodology learns the features of a local gate near the root node in the obfuscated design to predict the key of the locked netlist. This methodology is evaluated on different standard benchmark suites such as ISCAS-85, ITC-99, and EPFL. ORCA predicts the key with an average accuracy of 96.69%, outperforming the state-of-the-art deep learning oracle-less attacks SAIL, SnapShot, OMLA, and LIPSTICK by 21.28%, 15.43%, 9.11%, and 0.75%, respectively. To check the effectiveness of ORCA in real scenarios, it is evaluated on netlists synthesized using the complete technology libraries of different foundries, such as TSMC (40nm, 65nm, and 90nm) and GlobalFoundries (40nm), unlike the limited standard cells used in the state-of-the-art attack methods. In the case of a complete technology library, our attack methodology predicts the correct key with an average KPA of more than 70%, demonstrating that it can perform well even when the locked netlist is synthesized using the entire technology library. In addition to traditional Random Logic Locking (RLL), the proposed methodology is also tested on the ML-resilient DECOR logic locking scheme, which predicts the key with an average KPA of 69.61%, outperforming OMLA by 17.18%. In addition to key prediction, the locked netlist is converted to RTL, making ORCA a complete reverse engineering attack flow.
Modern low-power wireless communication systems often operate under strict energy and area constraints, especially in edge and embedded platforms. This article proposes novel optimization techniques for Multi-Level-Cell STT-MRAM (MLC STT-MRAM), replacing SRAM for an area- and energy-efficient Viterbi decoder in wireless communication. Three key techniques are introduced to mitigate the performance and energy consumption overhead of MLC STT-MRAM while preserving its high area efficiency. First, the energy barrier optimization technique is proposed, leveraging the fact that the survivor memory of the Viterbi decoder does not need to hold its data for a long period. This optimization significantly reduces the write energy. Second, the sequential-access-aware cell-split-mapping (SAA CSM) method exploits the sequential memory write and read access patterns of the Viterbi decoder, enabling a 1-step write. Third, the column-selective read technique utilizes column multiplexers within the memory peripheral circuits, eliminating unnecessary read operations and their associated circuits, thereby reducing power consumption and area. The proposed Viterbi decoder, compatible with IEEE 802.11n/ac, is implemented in a 28-nm CMOS technology, achieving 17.24% area and 55.15% energy reduction compared with a conventional MLC STT-MRAM-based design. Even compared with the conventional 6T SRAM-based design, the proposed design achieves 51.94% and 9.09% reduction in area and energy consumption, respectively, without performance degradation.
Deoxyribonucleic Acid (DNA) storage is promising to be an ultimate data storage solution with ultra-high storage density and long durability. A DNA storage system encodes and stores digital data with synthetic DNA sequences, and decodes DNA sequences back to digital data via DNA sequencing. Using primers and polymerase chain reaction (PCR) based random access has also been introduced to DNA storage for efficient data retrieval. However, a DNA storage system equipped with PCR-based random access suffers from primer-payload collisions. Primers with this type of collisions cannot be reliably used and must be discarded. Since the numer of usable primers determines the DNA tube capacity, it is critical to reduce the impact of primer-payload collisions and increase the tube capacity. In this paper, we propose to use variable length payloads to recover primers from collisions and enhance DNA storage capacity. With the proposed heuristic algorithms and four payload lengths, the scheme can recover thousands of collided primers with three state-of-the-art encoding schemes. For an existing collision resistant encoding scheme, Rotation code, it can further improve 18.27% of tube capacity, from 217.59 GB to 257.35 GB. For the other two encoding schemes, the improvements of tube capacity are 4.3X and 18,3X. respectively.
Hyperdimensional Computing (HDC), a brain-inspired Machine Learning (ML) technique, excels in edge computing due to its low resource requirement and is now advancing to handle even data-center workloads. By harnessing the advantages of photonics, high-speed and energy-efficient HDC training and inference can be achieved, fostering rapid HDC development. This article introduces PhotoHDC, the first electro-photonic accelerator designed for HDC training and inference, supporting traditional, record-based, and graph encoding. Our microarchitecture employs Mach-Zehnder Modulators and photodetectors to enable high-speed modulation with efficient dataflows optimized for HDC operations. We demonstrate that PhotoHDC can achieve one to four orders of magnitude lower Energy-Delay Product (EDP) than leading electro-photonic Deep Neural Network (DNN) accelerators when running HDC training and inference on popular datasets. We also show that photonics can address the limitations of compute-in-memory-based HDC accelerators, achieving three orders of magnitude lower EDP on average for both training and inference.
In the field of computer science, Convolutional Neural Network (CNN) algorithms are a crucial tool that contributes to the advancement of Computer Vision. CNNs are composed of an enormous number of multiplication and addition operations performed on the input data to calculate the probability and predict the output. In multiplication, if any of the operands is zero-valued, then it is irrelevant in that particular output, and hence, these computations can be omitted to avoid unnecessary computation. In this study, we propose an architecture that performs the computations through parallel Processing Elements(PEs) and is also capable of skipping the ineffectual zero-valued computation to improve PE utilisation. Our proposed work, SpALEn, adopts the channel-first dataflow and is designed to perform the inference function with zero-skipping for enhanced performance. Moreover, due to the skipped computation, load imbalance occurs as the computation workload varies among the PEs. A dynamic logic is designed to mitigate this and ensure the hardware resources are utilised thoroughly. SpALEn achieves a speedup of 12 \(\times\) in comparison to a dense architecture.
