Artificial intelligence (AI) has transformed domains from language to vision, but its rapid growth has led to soaring computational and energy demands that threaten sustainability. At the heart of these workloads are matrix-vector multiplications (MVMs) and nonlinear functions such as Softmax Activation (SMA), which dominate both runtime and power. Transformer models exemplify this challenge, where massive parameter counts and long sequence lengths make MVM and SMA critical bottlenecks. While silicon photonics (SiPh) promises massive bandwidth, low latency, and low power, existing accelerators remain limited to unsigned MVM and rely on CMOS for SMA, incurring repeated E/O conversions and lost efficiency. We present SUSTAINPHOT, a sustainable analog silicon photonic accelerator for large-scale AI training/inference that unifies two key innovations. First, SOFTONIC implements the first fully photonic Softmax engine, with decomposition, polynomial, scaling, and division units that natively compute SMA. Second, MIRAGE realizes a microring-based signed MVM architecture with built-in phase-error compensation, enabling accurate, full-range computation without duplicating weight banks or bulky equalizers. Together, these components form an end-to-end photonic pipeline that reduces energy and carbon footprint while sustaining accuracy and scalability. Co-simulations with commercial CAD tools demonstrate up to 80% lower power, 109x lower latency, and 199x higher compute density for SMA, while MVM achieves 34 ps latency, 39 fJ/MAC energy, and BER < 3 x 10(-4) under variations. By combining efficiency with resilience, SUSTAINPHOT establishes a path toward light-speed, energy-aware, and environmentally sustainable AI training.
Log-structured storage has emerged as a prevalent paradigm in the storage domain. However, the out-of-place update mechanism generates a substantial number of invalid data blocks, and the garbage collection (GC) mechanism employed to reclaim these blocks exacerbates write amplification. Although numerous existing schemes have made significant progress in mitigating write amplification, they often incur considerable performance and memory overheads. To address this issue, we present NatSep, a novel data placement scheme that reduces write amplification while safeguarding system performance and minimizing memory overhead. The core of NatSep lies in leveraging Native Information to characterize data hotness, with the following key design components: Firstly, NatSep meticulously defines the temperature regions and implements a strict rollback-style, unidirectional linear growth writing mode for each region. Secondly, NatSep adopts a more stringent GC selection strategy, for GC within a region, it strictly retrieves from the head of each region, and for GC between regions, there are priorities. Thirdly, NatSep manages each hotness temperature region independently and establishes dynamically allocated regions for adjacent temperature regions. The experimental results demonstrate that NatSep exhibits outstanding performance advantages compared with the current state-of-the-art data placement schemes. In detail, the throughput of NatSep has increased by 26%, the memory overhead has been reduced by 50.8%, and the performance has been improved by 20.6%.
Logic built-in self-test (LBIST) suffers from excessive power consumption due to high toggling rates caused by pseudo-random patterns. This paper presents a programmable low-power LBIST scheme that leverages scan chain weighting based on ATPG-guided fault analysis. By analyzing the distribution of specified bits across ATPG-generated test cubes, each scan chain is assigned a weight indicating its relative contribution to fault detection. Chains are then grouped into seven activation levels, each mapped to a distinct toggle probability to balance power and test coverage. A configurable control circuit based on shift and hold registers generates the required low-power signals. Experimental results on industrial-scale designs demonstrate that the proposed method achieves significantly higher fault coverage under identical power constraints compared to a commercial LBIST solution.
Representation learning has become an effective technique utilized by electronic design automation (EDA) algorithms. By addressing challenges related to the increasing complexity of circuits and the corresponding stringent power, performance, and area (PPA) requirements, representation learning facilitates the automatic extraction of meaningful features from complex data formats, including images, grids, and graphs. In this paper, the application of representation learning to digital IC design automation is explored with an analysis of prior work on foundational concepts and case studies on tasks that include timing prediction and routability analysis. Key techniques, including image-based methods, graph-based approaches, and hybrid multimodal solutions, are described that highlight the improvements provided in routing and timing prediction. The provided advancements demonstrate the potential of representation learning to enhance efficiency, accuracy, and scalability in current integrated circuit design flows.
As quantum computing advances, quantum circuit simulators serve as critical tools to bridge the current gap caused by limited quantum hardware availability. These simulators are typically deployed on cloud platforms, where users submit proprietary circuit designs for simulation. In this work, we demonstrate a novel timing side-channel attack targeting cloud-based quantum simulators. A co-located malicious process can observe fine-grained execution timing patterns to extract sensitive information about concurrently running quantum circuits. We systematically analyze simulator behavior using the QASMBench benchmark suite, profiling timing and memory characteristics across various circuit executions. Our experimental results show that timing profiles exhibit circuit-dependent patterns that can be effectively classified using pattern recognition techniques, enabling the adversary to infer circuit identities and compromise user confidentiality. We were able to achieve 88 % to 99.9 % identification rate of quantum circuits based on different datasets. This work highlights previously unexplored security risks in quantum simulation environments and calls for stronger isolation mechanisms to protect user workloads.
Photonic tensor cores have grown in popularity over the past few years for accelerating tensor-based kernels found in abundance in deep learning workloads because they offer potentially massive spatial parallelism (across wavelengths and waveguides), subnanosecond-scale start-to-solution latency, and near-dissipation-free dynamic operation. However, several shortcomings severely limit the practically achievable parallelism, processing throughput, and energy efficiency in existing photonic tensor core architectures. For instance, the wavelength-selective analog operation of existing designs makes them highly prone to crosstalk noise and other optical signal penalties and losses. These penalties and losses interplay with an already tight optical power budget, leading to strong trade-offs for achievable spatial parallelism, operating data rate, and analog precision. This paper shows how co-designing low-dissipation, low-noise, and high-speed electro-photonic devices, crosstalk-minimal circuit organizations, and mixed unary/analog signaling methods can overcome these shortcomings to realize photonic tensor cores with scaled-up throughput and operational energy-efficiency benefits for accelerating a variety of deep learning workloads.
The rapid expansion of distributed and edge computing platforms—spanning autonomous vehicles, IoT sensors, and healthcare monitors—has heightened concerns about data privacy. Differential Privacy (DP) offers a rigorous mathematical framework to protect sensitive information while retaining analytical utility. This tutorial introduces the foundations of DP for both numerical and categorical datasets and extends the discussion to correlation-aware techniques tailored for structured and high-dimensional data. Hands-on demonstrations will begin with the PETINA (Privacy prEservaTIoN Algorithms) package for numerical data and continue with MIC-DP (Maximum Information Correlated Differential Privacy) for tabular data. Designed for researchers and practitioners in secure systems, embedded architectures, and AI accelerators, the tutorial emphasizes practical and scalable methods for integrating DP into real-world system designs.
For low-power designs utilizing multiple threshold voltage (VT) levels such as using a mixture of regular, low, and super-low VT standard cells, a small perturbation on each VT level leads to a significant fluctuation of the leakage power consumption. In this context, this work addresses the problem of finding the value of each VT level on the target design with the objective of minimizing the total leakage power consumption of the design. Precisely, for a timing closed design, typically at the post-route stage, whose leakage power has already been optimized for a representative (i.e., nominal) value of each VT level, we explore the range of VT level values and fine-tune the VT values, so that the resulting leakage power of the design should be further minimized while not violating the timing constraints. To this end, we propose a near-optimal approximation technique based on a piecewise-linear programming formulation for the VT reassignment, incorporating the practical issue of circuit delay and leakage power recalculation incurred by VT tuning into linear programming constraints and objective. In the meantime, through experiments with benchmark circuits, it is shown that our VT tuning technique is five orders of magnitude faster than the conventional VT tuning while further reducing the leakage power by 5.41% under the circuit timing constraints.
In computer systems, fair-share scheduling of resources is essential, and virtual time-based algorithms are widely adopted for their work-conserving nature. These algorithms rely on tracking the minimum virtual time, as they always schedule the entity with the smallest value to ensure fairness. Maintaining this minimum efficiently is crucial for scalable performance, particularly in multi-core systems where contention can be high. Mindicator, a scalable and low-overhead data structure, is wellsuited for tracking minimum values and is a natural candidate for monitoring minimum virtual time. However, its use in virtual time management is limited because virtual time grows monotonically and can exceed the 32-bit integer range supported by Mindicator. This leads to incorrect minimum tracking when values overflow, potentially causing fairness violations and even malfunctioning behavior. To overcome these limitations, this paper proposes TMindicator (Twin-Mindicator), a scalable approach to virtual time tracking that tolerates integer overflow and supports values with arbitrary bit widths. T-Mindicator uses two Mindicator instances, each managing a 32-bit value, while independently tracking the number of even and odd overflow events. By concatenating the overflow counters with the 32-bit minimum values from each instance, T-Mindicator effectively extends support to 64-bit and larger virtual time representations. Our evaluation demonstrates that T-Mindicator preserves fairness among competing entities and ensures stable workload execution without anomalies when integrated into a state-of-the-art fair I/O scheduler.
Modern data-centric workloads are driving rapid growth in the demand for high-bandwidth, large-capacity memory. Compute Express Link (CXL) has emerged as a key technology for scalable memory expansion through the Peripheral Component Interconnect Express (PCIe)'s high-speed serial interfaces. However, while PCIe 6.0's L0p mode enables lane-level power gating without disrupting traffic flow, it lacks a policy mechanism for dynamically deciding the number of active lanes. Since actual energy savings depend on matching active lanes to runtime bandwidth demand, such a policy is essential. This paper presents DDLM (Demand-Aware Dynamic Link Width Management), a lightweight control framework that improves CXL link energy efficiency by dynamically adjusting link width based on runtime traffic. DDLM integrates two complementary modules: a predictor that predicts bandwidth demand based on short-term temporal locality to set the width ahead of hardware transition latency, and a congestion monitor that detects transient congestion via internal queue inspection. These modules are coordinated by a finite state machine that manages safe link width transitions under physical-layer constraints. We implement DDLM in the Ramulator2 simulator and evaluate it with diverse SPEC CPU workloads. Compared to a fixed-width baseline, DDLM reduces CXL Memory energy by up to 13%, improves utilization by 2.22x, and limits performance loss to under 3%. This work offers a practical path to energy-proportional CXL Memory.
Quantum computing offers speedups, but NISQ processors face hardware-induced errors that degrade fidelity and reproducibility. We introduce an uncertainty-aware benchmarking framework that combines uncertainty quantification with global sensitivity analysis to evaluate not only peak fidelity but also its reliability over time. Using Bayesian Optimization with SGLD refinement under fixed budgets, seeds, bounds, and trust-region rules, and repeating runs across days, we capture calibration drift and quantify efficiency, stability, landscape complexity, and maintenance cost. A noise-aware Gaussian process surrogate provides scalable sensitivity estimates without error mitigation. Applied to VQAMET and VQC on three IBMQ backends, the framework delivers actionable guidance for co-tuning and backend selection, complementing and often outperforming quantum volume style metrics.
Hyperdimensional Computing (HDC) has emerged as a hardware-efficient paradigm for embedded malware detection, offering strong parallelism and low complexity. However, the accuracy and robustness of HDC classifiers remain highly dependent on the diversity and quality of training data, leaving them vulnerable to novel threats. To address this challenge, we introduce a generative adversarial network (GAN)-assisted augmentation framework for the Microprocessor without Inter-locked Pipelined Stages-32 (MIPS32) malware generation. The GAN is trained on real-world MIPS32 malware binaries to produce previously unseen instruction sequences. The synthetic code stacks are filtered using a custom MIPS32 assembler for syntactic validation and a Bidirectional Long Short-Term Memory (BiLSTM)-based semantic critic to ensure logical coherence. Only validated samples are retained to expand the training set for the HDC classifier, thereby strengthening generalization and resilience against novel malware variants. Our preliminary results show an average generator loss (G) of 2.68 over 200 epochs and a discriminator loss (D) converging to 0.63, indicating that the GAN is learning to generate realistic and diverse outputs. This hybrid GAN-BiLSTM-HDC framework shows strong potential for enhancing classification accuracy, resilience, and efficiency in resource-constrained, real-time malware detection systems.
Coarse-Grained Reconfigurable Architectures (CGRAs) have emerged as promising solutions for energy-efficient computing in edge devices and datacenter accelerators. While offering substantial performance benefits, their adoption is hindered by the NP-hard loop mapping problem during compilation. In this paper, we present NAVIMAP, a neural-symbolic framework combining partial order-aware graph embeddings with deep reinforcement learning. Experimental results demonstrate that NaviMap achieves a 1.95x speedup in solving CGRA mapping problems compared with state-of-the-art methods, while producing mappings with equivalent or superior performance.
Persistent memory (PM) offers a compelling combination of durability and near-DRAM performance, but it also introduces new challenges for hashing indexes. Existing persistent hashing designs prioritize resizing efficiency at the expense of increased query latency, losing the key advantage of hash tables. This paper introduces R(2)Hash, a persistent hashing index redesigned from the persistent cache-line hash table, to balance high read performance with efficient resizing. R(2)Hash is guided by a migration rule, enabling it to meet both goals through two main contributions: (i) a cooperative and low-overhead resizing strategy based on split-order hashing, and (ii) a shift-aware search combined with a two-layer bucket layout that enables lock-free reads with only one PM access on average. Furthermore, R(2)Hash provides log-free consistency and a non-blocking recovery mechanism. Experimental results demonstrate that R(2)Hash achieves up to 8.1x higher search throughput and 7.5x higher insert throughput compared to other persistent hash indexes across a range of workloads.
Speculative execution attacks exploit malicious speculation to leak sensitive data via microarchitectural covert channels. Speculative Taint Tracking (STT) is a state-of-the-art hardware mechanism that blocks such threats by tainting data flowing from speculative loads, untainting data once all its dependencies are not speculative, and delaying instructions that create covert channels until their inputs are untainted. However, STT's hardware feasibility remains unclear due to a lack of detailed hardware cost analysis. This paper presents the first in-depth hardware cost analysis of STT and identifies two key challenges: (1) the logic delay of taint propagation, which grows with rename width, and (2) area overhead from instruction delaying, which requires expensive CAM-style logic to enforce speculation safety. To address these, we propose a new microarchitecture for STT, called mu STT. mu STT is based on two new mechanisms. First, the Age Matrix is a shallow taint propagation circuit that removes 85% of the logic delay overhead of prior STT designs, while only adding 36% more area at the default rename width of 8. Second, the impede micro-op implements instruction delaying in a fashion that increases STT's performance overhead by only 5 percentage points (from 16% to 21%), while replacing bespoke STT hardware with existing RAWdependency tracking. Together, these contributions reduce STT's hardware complexity and cost in the context of high-end wide-issue processor designs.
With the advances of deep learning, efficient model inference is crucial. Deep learning compilers optimize inference by decomposing models into subgraphs and searching schedules for them, whose evaluation relies on accurate cost models. Existing methods suffer from high transformation overheads or limited prediction accuracy caused by insufficient structural representation of subgraphs and schedules. To address these limitations, we propose CAST, a framework that predicts schedule performance based on Abstract Syntax Trees (ASTs). CAST proposes AST classification based on structural similarity and class-specific cost models. Experiments show CAST achieves significantly reduced prediction errors and up to 13x higher efficiency than prior methods.
This paper presents TCFlash, a practical and immediately deployable technique for executing bulk bitwise operations directly within commercial off-the-shelf (COTS) 3D NAND flash chips, using only standard user-mode commands. TCFlash enables in-place bitwise computation by combining logical data encoding of triple level-cell (TLC) storage with dynamic read reference voltage shifting. We demonstrate TCFlash across multiple 3D TLC NAND devices spanning both floatinggate and charge-trap technologies from two major vendors. To our knowledge, this is the first on-chip demonstration of error-free bitwise operations in 3D NAND. Experimental evaluation across vertical layers in the 3D NAND stack shows that TCFlash achieves zero raw bit error rate (RBER) for two-operand OR, AND, and XNOR operations, and RBER is below 0.006% for NAND, NOR, and XOR. Additionally, for the first time, we also demonstrate simultaneous three-operand bitwise operations with RBER below 0.008%.
Embedding aggregation in large-scale recommendation systems creates severe memory bandwidth bottlenecks, as each query sums many high-dimensional vectors. Bitwise-operation-based PIM can exploit subarray bandwidth, but traditional designs struggle with summation because long carry propagation limits parallelism. We propose PIM-SUM, an in-DRAM summation primitive for Sparse Length Sum (SLS) in recommendation workloads. PIM-SUM reformulates vector summation as column-wise accumulation via popcount, truncating carry propagation and avoiding redundant in-DRAM computation. This enables high-throughput summation using native DRAM bitwise primitives. PIM-SUM integrates a Reed-Solomon-inspired error correction at the DRAM row level. Its linearity supports parity propagation, enabling integrity checking and multi-bit error correction with low overhead. On DLRM workloads, PIM-SUM achieves up to 5.14x speedup, logarithmic I/O reduction, and large energy savings. It also reduces silent data corruption by 1778x and improves detection by over 170x. These results show PIM-SUM is a scalable, fault-tolerant, and energy-efficient solution for memory-bound inference at data center scale.
The block-based inference engine, powered by non-contiguous key-value (KV) cache management, has emerged as a new paradigm for large language model (LLM) inference due to its efficient memory utilization. However, in large-batch, long-context workloads, the substantial demand for KV cache remains a major bottleneck in inference performance. Existing research leverages the sparsity of the attention mechanisms by removing non-critical tokens to limit the KV cache size. However, we observe that in block-based inference engines, current sparse methods require defragmentation after token removal to maintain tensor continuity, incurring significant overhead. Additionally, we find a correlation between request length and sparsity potential, yet existing methods apply a uniform sparsity strategy at batch level without dynamic adjustment. To address these, we propose DualSpar, a novel sparse KV cache framework with dual-granularity memory and adaptive sparsity strategy. First, it binds token importance to KV cache block granularity, achieving low-overhead pre-consolidation. Second, it incorporates system load and request length into sparsity decision, fully exploiting the sparse potential of different requests while reducing the queuing latency in large-batch processing. Evaluations show that DualSpar achieves up to a 3.16x throughput improvement, a 3.75x faster time-to-first-token (TTFT), and an 87.2% reduction in defragmentation overhead while maintaining high accuracy.
Hardware-assisted in-process compartmentalization reduces attack surface at low cost, but existing methods face practical challenges: inefficient dynamic permission management, weak metadata/instruction protection, and limited resource isolation. To tackle these problems, this paper proposes DASICS, a lightweight and efficient design of hardware-assisted in-process compartmentalization. DASICS partitions the process code segments into trusted and untrusted compartments and implements a user-mode protection runtime in the trusted compartment for dynamic permission management. It employs boundary registers to enforce dynamic access-control restrictions on instructions within different untrusted compartments. Additionally, it applies metadata access restriction, control-flow checks, and systemcall filtering for the untrusted compartments to achieve comprehensive protection. We implemented a hardware prototype of DASICS on the RISC-V XiangShan superscalar out-of-order processor and validated its effectiveness on FPGA. Our prototype increases less than 5% LUTs cost, and experimental results show that DASICS isolation incurs an average overhead of 6.02% on Memcached key-value store and 8.18% on NGINX webserver. DASICS project is publicly available at github.com/DASICS-ICT.
