Edge acceleration for large language models (LLMs), particularly improving generation speed during decoding, is critical to their widespread application. However, achieving fast attention inference and efficient decoding on resource-constrained edge accelerators remains challenging. This brief presents SwiftKV, a co-designed edge-oriented attention algorithm (SwiftKV attention) and multihead accelerator (SwiftKV-MHA). SwiftKV attention is a per-token pipelined, single-pass attention algorithm that processes each $(k_{t}, v_{t})$ in the KV cache exactly once in a uniform per-token pipeline, without score materialization, blockwise softmax, or a second pass, enabling fast attention on edge accelerators without relying on resource-intensive parallelism. To further accelerate end-to-end decoding and address the limited multihead support in existing accelerators, SwiftKV-MHA supports high-precision attention and low-precision GEMV on the same processor array, enables multihead parallel inference, and allows each processor to complete all operations for single-head independently, thereby achieving fast and efficient decoding. Experimental results show that, on the Xilinx Alveo U55C, the SwiftKV attention achieves a $7.16\times $ speedup over native attention and significantly outperforms prior attention algorithms. In SwiftKV-MHA, attention accounts for only 3.19% of the end-to-end inference latency; under the same settings, it improves generation speed by 17.4% and increases efficiency by $1.98\times $ compared to state-of-the-art works.
Spiking neural networks (SNNs) enable efficient on-chip learning but face a critical hardware challenge due to the computational asymmetry between small-kernel convolution operations in the feed-forward (FF) stage and large-kernel ones in the weight-gradient (WG) stage. Directly mapping these conflicting patterns onto a static architecture disrupts data locality, typically necessitating either disjoint processing units or redundant data movement, which severely compromises energy efficiency. This brief presents an architecture for unified learning in SNN (AULiS), a sparsity-aware accelerator supporting low-cost BFloat16 local learning (LL) via reconfigurable engines. Its core innovation is an algorithm-architecture codesign. We reformulate the WG stage into broadcast multiplications and map it to an output-stationary (OS) dataflow, newly applied to WG, complementing the weight-stationary (WS) dataflow used for FF. This strategy matches the distinct data-reuse characteristics of each stage: locking weights during FF and weight gradients during WG, allowing a single reconfigurable engine to process both, thereby minimizing data access and maximizing compute density and energy efficiency. Implemented in a 28-nm process, AULiS occupies 2.24 mm2 and achieves this unification with only a 3.4% area overhead. The architecture reaches 23.0 TFLOPS/W in inference and 22.3 TFLOPS/W in training, in dense-equivalent FLOPs at 95% zero sparsity. In a fair comparison, this represents a $3.78\times $ training and $1.50\times $ inference improvement in normalized energy efficiency over prior SOTA while delivering up to $10.64\times $ higher normalized compute density. The high and balanced efficiencies prove that learning can be unified with high-performance inference without efficiency compromise for adaptive edge artificial intelligence (AI).
The Hamming quasicyclic (HQC) scheme has been selected by NIST for standardization in postquantum cryptography (PQC). The hardware implementations of HQC face challenges, including high latency, significant hardware overhead, and insufficient system-level scheduling optimization. To address these challenges, an area-efficient HQC hardware accelerator is proposed, in which the architecture of critical computational modules is optimized, and system-level scheduling is comprehensively enhanced. In particular, a unified and parallel sampling module (PSM) is first proposed. By incorporating only a small amount of detection logic, the sampling latency is significantly reduced. Moreover, the PSM supports both constant weight word (CWW) and fast nonbiased (FNB) modes. Subsequently, a novel, unified, four-way parallel polynomial arithmetic module (PPAM) is proposed. An innovative shared register bank design is proposed, which effectively reduces BRAM overhead. In addition, the PPAM supports both polynomial addition and multiplication modes. Finally, to address the challenge of insufficient system scheduling optimization, a fine-grained overlapped execution scheme (FGOES) is proposed, which further increases the execution overlap among modules and reduces the overall system latency. The proposed architecture is verified on an Xilinx Artix-7 field-programmable gate array (FPGA). Under the three NIST security levels, compared with state-of-the-art designs, the area-time product (ATP) is improved by $2.05\times $ to $11.02\times $ , $2.33\times $ , and $2.25\times $ , respectively.
Reliable fall detection is important for elderly care and daily monitoring, yet continuous radar-based systems remain challenged by false alarms and energy overhead under resource-constrained deployment. This brief presents a radar accelerator through algorithm–hardware codesign for continuous fall detection. A hardware-friendly centroid-descending detector (CDD) is introduced to reject obvious nonfall segments before neural inference, thereby reducing unnecessary computation during continuous monitoring. For refined classification, a lightweight spatio-temporal convolutional neural network (CNN), termed Light-STNet, is developed for low-complexity fall recognition. A dedicated accelerator architecture is further designed to support efficient heterogeneous processing. Implemented for the Xilinx Zynq ZC702 platform using only 6.46 K LUTs and seven DSPs, and further evaluated through a 65-nm postlayout implementation, the proposed design retains 99.43% accuracy after groupwise 4-bit quantization (versus 99.71% in floating point) while occupying 0.394 mm2 and consuming 14.78 mW at 100 MHz, demonstrating an efficient solution for low-power continuous fall detection.
Digital power control applications impose stringent real-time computational demands, particularly for trigonometric operations in closed-loop systems. To address this challenge, we propose a domain-specific RISC-V controller for digital power (DSRVC-DP), a customized controller based on the tinyriscv open-source processor. The design extends the RISC-V instruction set with hardware-accelerated trigonometric operations via a memoized CORDIC unit, which exploits data reuse to eliminate redundant iterations. Experimental results demonstrate substantial improvements over DSP and ARM controllers. Single-angle evaluation and trigonometric-table generation are significantly accelerated, and the interrupt service routine (ISR) execution time in closed-loop control is reduced by 48% and 27% in inverter control, and by 36% and 11% in the phase-locked-loop (PLL) applications, respectively. These results confirm DSRVC-DP’s effectiveness in enhancing real-time performance for digital power control.
