This brief presents a dynamic buffer with a built-in track-and-hold (T/H) targeting high-speed, moderate-resolution time-interleaved analog-to-digital converters (TI-ADCs). The proposed buffer employs an open-loop push–pull source follower (PPSF) powered by a floating battery capacitor for dynamic biasing, enabling energy-efficient T/H operation without external sampling switches or common-mode feedback (CMFB). Adynamic self-adaptive current-compensation (DSACC) path is included to enhance linearity with minimal overhead. Fabricated in 28-nm CMOS, the prototype occupies 0.003 $\text {mm}^{{2}}$ and consumes 2.3mW. Silicon validation is performed by integrating the buffer into a heavy-loading 6-bit, 9.3-GS/s TI-FLASH ADC. Achieving 41.1dB SFDR and 31.0dB SNDR via indirect system-level measurement demonstrates robust high-speed driving capability for moderate-resolution applications.
SRAM compute-in-memory (CIM) macros activate tens to hundreds of wordlines at once, drawing large currents that cause a severe resistive voltage drop across the power delivery network (PDN). We model this with quasi-static active-transistor PDN (QS-ATP), the first model to cosolve, across supply and ground, all three series IR-drop components of an SRAM CIM macro (power mesh, internal Met1/Met2 rail, and footer), with the two-transistor cells and footers as nonlinear self-limiting devices. GPU-solved in double precision, it matches full-6T HSPICE within ~1.48%VDD up to a $256{\,} \times{\,} 256$ array. Calibrated to the 130-nm foundry node (Sky130), it evaluates power integrity at 130, 7, and 5 nm. At each node, the peak drop reaches 61%–68% of the supply, dominated by the internal subarray rail, whose resistance grows with scaling and which backside power delivery network, removing only the mesh drop, leaves intact. Array partitioning, which shortens that rail, is the effective mitigation. Under a fixed metal budget, it raises the worst case effective cell voltage by 26% and nearly eliminates the read-current spread at 130 nm, with the same trend at 7 and 5 nm. Partitioning recovers the read-current-attenuation accuracy loss without retraining, returning binary MNIST, multibit CIFAR-100, and multibit ImageNet-1k networks to within 0.2 points of their ideal accuracy at 130 nm. At 7 and 5 nm, partitioning alone leaves the worst cell barely above (7 nm) or even below (5 nm) the read-retention voltage at full supply, so both are paired with wordline-voltage scaling, widening the margin beyond 400 mV.
This work presents a dynamic-threshold true random number generator (DT-TRNG) that improves entropy extraction and process, voltage, and temperature (PVT) tolerance through substrate-bias compensation (SBC). The proposed entropy source integrates resistors with dynamic-threshold MOS (DTMOS) modulation to amplify intrinsic thermal noise. A lightweight digital-to-analog converter calibrates source mismatch before raw-bit sampling. Fabricated in a 180-nm CMOS process, the prototype occupies a normalized area of 0.11063 MF2. At 0.7 V, it consumes $2.76~\mu $ W, delivers 16.83 Mb/s, and achieves an energy efficiency of 0.164 pJ/bit. Measured full-grid PVT entropy-map results from 0.7 to 1.4 V and $- 40~{^{\circ } \mathrm {C}}$ to $120~{^{\circ } \mathrm {C}}$ show a calibrated zero/one ratio of 49.4%–50.6% and a calculated min-entropy above 0.992 using one nominal SBC code. The raw outputs pass the NIST SP 800-22 suite and satisfy the NIST SP 800-90B evaluation. Restart screening across nine chips, using 32 restarts per chip and a 100-kbit sequence per restart, evaluates 4464 sequence pairs, with all per-chip maxima remaining below the $4/\sqrt {N}$ screening bound. The proposed design demonstrates excellent tolerance to PVT variations.
This article proposes a capacitorless low dropout regulator (LDO) with a hybrid gate-drive (HGD) scheme to achieve fast transient response and stable operation in wireless power transfer (WPT) receivers where the use of external output capacitors is limited. The proposed LDO enhances the transient response through an HGD structure that combines an adaptive buffer and a dynamic current injection circuit (DCIC). In the steady state, the adaptive buffer provides load-dependent gate drive, whereas during transients, the DCIC is instantaneously activated to provide feedforward compensation. The proposed LDO is fabricated in a 0.13- $\mu $ m BCD process and operates at a dropout voltage of 200 mV. For a load transition up to 100 mA, measurement results show an overshoot of 128 mV, an undershoot of 157 mV, and a settling time of 740 ns with a 100-ns edge time. Furthermore, the proposed LDO features a line regulation of 4.94 mV/V and a load regulation of $155~\mu $ V/mA.
Reduced instruction set computer V (RISC-V) has recently emerged as a popular open-source instruction set architecture (ISA) for designing high-performance processors with low-power requirements to meet the demands of edge computing. In this article, we present a novel dual-issue RISC-V core for edge-computing applications. The proposed core employs a selective-bypass mechanism to effectively improve performance by supporting the single-cycle execution (EX) of selected pairs of data-dependent arithmetic instructions. The results show that the proposed core achieves a frequency of 1587 MHz, an area of 0.045 mm2, and a dynamic power consumption of $42.7~\mu $ W/MHz in a 28-nm CMOS process. Compared with the baseline version, the proposed core achieves a performance improvement of 7.5% in CoreMark/MHz. The CoreMark and Dhrystone benchmark scores of the core are 4.32 CoreMark/MHz and 2.67 DMIPS/MHz, respectively, which are 24.5% and 32.2% higher than those of the ARM Cortex-R5. The proposed core achieves up to a 56.5% improvement in CoreMark/MHz compared with state-of-the-art commercial and RISC-V cores targeting edge-computing applications.
