Dual (DMR) and Triple Modular Redundancy (TMR) are widely used techniques to provide fault detection and/or tolerance capabilities in safety-critical systems through - often diverse - redundancy. However, these systems remain vulnerable to adversarial attacks, which can mislead the AI models and lead to severe consequences. In this paper, we propose enhanced DMR and TMR implementations for image-based object detection leveraging image transformations during inference to mitigate the impact of adversarial attacks, hence addressing safety and security concerns simultaneously. Our approach achieves up to 12.9% and 12.2% higher accuracy in adversarial scenarios compared to stateof-the-art solutions in DMR and TMR configurations, respectively.
The relationship between cybersecurity and digital sovereignty is increasingly viewed as complementary. Cybersecurity focuses on the technical and operational protection of digital infrastructures, while digital sovereignty encompasses the political and strategic dimensions related to technological autonomy and the ability to regulate and make decisions. This intersection is particularly noticeable in technology and regulation-heavy sectors, such as the automotive industry, where vehicles are transforming into connected and intelligent platforms capable of generating, processing, and transmitting large amounts of data. In this context, protecting user privacy emerges as a critical challenge, closely linked to cybersecurity needs and the control over the cross-border flow of information. These dynamics show how difficult it is to coordinate cybersecurity, data management, and compliance across different countries, especially when foreign suppliers and supply chains are involved. Consequently, there is an urgent need for a coherent, shared, and relevant technical-conceptual framework that integrates operational requirements, fundamental rights, and strategic objectives. This paper proposes a semantic approach to analyze, systematize, and map emerging key concepts from normative sources, policy documents, and standards, using both expert-based approach and Artificial Intelligence models, to facilitate the extraction and organization of domain-specific terminology enhancing the population or enrichment of semantic resources. Results show the importance of controlled vocabularies, such as thesauri, which serve as fundamental tools for facilitating classification, interoperability, and for supporting normative production. In the case of the automotive sector, it becomes an operational support to address challenges related to cybersecurity, privacy protection, and regulatory autonomy.
Content Addressable Memory enables high-speed binary pattern matching and is widely used in various applications. Exploiting Resistive Random Access Memory (ReRAM) for CAM (ReCAM) realization offers advantages in terms of non-volatility, high density, and low power consumption using the Computation in Memory (CiM) concept. However, the unique defects of ReRAM combined with CMOS fabrication defects, introduce new faulty behaviors that complicate detection and diagnosis, thereby increasing the risk of test escapes and field failures. However, diagnosing faulty cells in ReCAM is crucial for analyzing failure mode, which helps improve manufacturing yield. It also promotes defect and fault tolerance both post-manufacturing and during runtime. Pinpointing faulty cells within the ReCAM array is particularly challenging, especially when all cells are connected to the same match-line (ML). Diagnosis also plays a critical role at runtime by enabling fault tolerance through mechanisms such as bypassing defective cells. This paper proposes a novel Design-for-Testability (DfT) approach for ReCAM diagnosis that utilizes infinitesimal voltage differences to identify the location of faulty cells. The proposed DfT circuitry and the accompanied diagnosis flow enhance diagnostic precision by enabling adjustable gain and sampling time in a multi-step process, effectively identifying faulty cells within the array. The simulation results of two distinct fault scenarios, applied to the binary patterns of all-match and all-mismatch conditions, demonstrate the effectiveness of the proposed DfT technique in achieving fine-grained fault detection across the ReCAM array. Furthermore, using this approach reduces the time complexity by more than half compared to the March-based approach with negligible overhead in area and power.
Convolutional Neural Networks (CNN), particularly those used in critical applications, such as autonomous driving, medical systems, and aerospace, require high reliability. While these algorithms exhibit inherent resilience, they remain sus-ceptible to Single-Event Effects (SEE) occurring at the hard-ware and impacting the model execution. These effects, usually induced by interactions with radiation particles, can lead to errors in electronic components, potentially causing incorrect inferences and increasing the risk of mispredictions. Meanwhile, quantization and pruning are widely employed to reduce the hardware footprint of CNN models, facilitating their deployment on embedded systems. Even when the models are reduced, CNN remain too large for an exhaustive fault injection campaign to assess their resilience. To address these challenges, we propose SFI4NN, a Statistical Fault Injection (SFI) framework specifically designed to evaluate the fault sensitivity of fixed-point quantized and pruned CNN architectures. Furthermore, we analyze the model resilience as a function of the pruning rate, showing that CNN sensitivity increases as pruning becomes more aggressive. The obtained results enable the development of hardware hardening strategies with reduced costs that are tailored to the reliability requirements of targeted applications. Experimental results demonstrate a 96 % improvement in resilience, with minimal hardware overhead compared to conventional hardening techniques such as triplication.
The quest for reliable testing of analogue and mixed-signal circuits remains a cornerstone in the advancement of integrated circuit technology, driving innovation in high-stakes areas such as aerospace and automotive systems. The continuous nature of the signals and the variability of the components make the task both time consuming and difficult to automate. This work presents a general methodology to detect parametric faults in analogue circuits using machine learning models combined with Monte Carlo simulations, advanced signal transformations and optimal classifier selection. The proposed framework is adaptable to different circuit architectures, as demonstrated by simulations of RLC bandpass filters and Sallen-Key filters. In particular, our approach incorporates new metrics that balance classification accuracy with implementation complexity and computational efficiency, providing a scalable solution adapted for automation and integration into an embedded test environment.
