In this work, we demonstrated 3D sequential complementary field-effect-transistor (CFET) by direct wafer bonding (DWB) technique and a low-temperature process for monolithic 3D(M3D) integration using a high-performance top Ge (110)/<110> channel on bottom Si CMOS. Here, the maximum thermal budget was up to 400°c during the fabrication of top Ge FET, allowing high-performance heterogenous Ge/Si CFET without damage to bottom Si FETs. Furthermore, we systematically investigated the mobility enhancement to channel orientation in thin Ge (110) nanosheet channel pFET. Low effective hole mass along <110> direction on Ge (110), which was calculated by the k$\cdot$p method, provided record high mobility of approximately 400 cm2/V$\cdot$ s (corresponds to 743 cm2/V$\cdot$ s when normalized by footprint) among the reported Ge pFET with similar channel thicknesses at room temperature.
To continue contacted gate pitch scaling, transistor with improved electrostatics, gate stack innovation, and appropriate contact scheme along with improved process control to reduce variability are all indispensable factors. As gate pitch scales into the sub-50nm regime, electrostatics of FinFET architecture, spacer material, and traditional contact scheme all approach their engineering limits. Here we report a leading-edge CMOS technology developed at 45nm contacted gate pitch that successfully incorporates optimized fin profile, low-k spacer and self-aligned contact scheme. The process robustness is validated by a logic test chip with >3.5 billion transistor gate count and fully functioning 256Mb HC/HD SRAM macros. The demonstrated high-density SRAM cell size of $0.0199 \mu \mathrm{m}^{2}$ is the smallest reported to date.
Homomorphic encryption (HE) is an encryption technology of which encryption and decryption process can be summarized as polynomials modulo multiplication computing with noise. In this paper, HE is firstly implemented on resistive random-access memory (RRAM) arrays, which are utilized as both matrix-vector multiplication (MVM) units and true random number generators (TRNG). Both high stability and good randomness are achieved for MVM and TRNG, respectively, by using different forming schemes, so that two distinct functions can be realized using the same device. Furthermore, the encryption-decryption process for privacy-preserving cloud computing is experimentally implemented on a hardware system with eight 144Kb RRAM arrays. For the whole RRAM array-based encryption-decryption process, small accuracy losses of 0.73% (for SVM) and 1.9% (for CNN) are achieved. This is the first demonstration of encryption computing acceleration with emerging device technology.
A complete picture of the dynamics of the ferroelectric oxide/metal interface is presented, which unifies the main reliability issues, field cycling endurance, and retention for HfO 2 –based films in ferroelectric random-access memory. Together with a novel retention interpretation, the ferroelectric interface is established as the key component for pioneering HfO 2 -based ferroelectrics for commercial memories.
The recent huge success of AI requires the development of dedicated H/W solutions for massive basic arithmetic operations – multiply and accumulation (MAC). Inmemory computing is one of the most progressive attempts in AI acceleration. The key embodiment of in-memory computing is the crossbar array of conductive memories. The crossbar array stores neural net weights in situ and performs MAC operations in an analog manner to significantly reduce power consumption. Here we innovate device and circuit solutions to develop the first MRAM crossbar array using Samsung 28-nm embedded MRAM CMOS technology.
