Brain inspired in-memory computing using networks of analog non-volatile memory (NVM) elements has emerged as a promising, more energy efficient alternative to digital computing for data intensive applications [1] . Since information processing is performed in the analog domain, control of electrical noise in the NVM elements becomes critical for achieving optimum accuracy [2] [3] . Here, we compare the noise characteristics of two NVM device types with programming mechanisms that depend on ion motion: electrochemical random access memory (ECRAM) and filamentary resistive random access memory (ReRAM). [4] [5] [6] . Furthermore, we demonstrate that ECRAM with a VO 2 channel, a material that exhibits an insulator-to-metal transition (IMT), enables manipulation of the noise characteristics, which can be utilized for hardware implementation of Bayesian Neural Network [7] .
Analog in-memory computing with resistive memory devices is a compelling alternative to conventional digital von Neumann computers [1]. Recent advancements in learning algorithms and hardware optimizations have enabled the utilization of ReRAM technology for deep neural network training purposes [2], in addition to inference. Specifically, ReRAM devices based on Conductive-Metal-Oxide (CMO)/HfO x stacks exhibit lower programming stochasticity and finer conductance updates [3], [4]. The physical explanation of the enhanced device performance is still debated. Previous reports have attributed it to multiple filament switching [5], or to oxygen content modulation in the CMO region above a single filament [6]. To maximize the potential of this technology for both inference and training applications, a comprehensive understanding of the intrinsic sources of noise is required. Prior research on nanometer-scale devices has demonstrated noise properties being dependent on device resistance, frequency, and applied voltage [7], [8]. In particular, low-frequency noise measurements offer valuable insights into the electronic transport and noise-generating mechanisms. This study investigates read noise in CMO/HfO x ReRAM devices and compares it with other systems.
Dynamic random-access memory (DRAM) is popular as a main memory due to fast and reliable memory. DRAM has a simple architecture with only one transistor and one capacitor, making it low-power and highly integrated [1] . However, the DRAM cell faces some issues, such as current leakage at the nanoscale device level and the need for periodic refresh. To overcome these issues, researchers are looking into utilizing a floating body of single Silicon-on-Insulator (SOI) MOSFETs as charge storage [2] – [4] . The Capacitorless DRAM (1T DRAM) cell operations are based on charge (hole) generation and recombination [2] – [4] . Accumulation of holes in the floating body represents the state “1”, while evacuation of holes from the body is the state “0”. The difference between these states is termed the sensing margin ( SM ), and retention time ( T ret ) is evaluated at a time when the difference between these states reaches 50% of its maximum value [2] – [4] . In this work, we have proposed a new device design with an elongated storage region to improve the retention time of 1T DRAM cell at a shorter gate length and higher temperature.
Double spin torque magnetic tunnel junctions (dsMTJ) serve as advanced nonvolatile memory, impacting sectors like computing, automotive, and storage [1] . dsMTJs rely on a magnetic tunnel junction (MTJ) with a CoFeB reference (RL) and free layer (FL), separated by an MgO tunnel barrier (TB), improved with a second RL separated by a non-magnetic spacer (NMS). Yet, smaller devices face reliability issues, such as back-hopping from higher current densities, undermining memory stability [2] . Interlayer exchange coupling (IEC) is crucial for enhancing memory cell performance and stability in compact MTJ stacks, in order to achieve higher memory density and to overcome traditional architecture limitations, thereby boosting memory reliability and performance [3 , 4] .
Gallium Nitride (GaN) High Electron Mobility Transistors (HEMTs) are pivotal for next-generation power switching applications due to their wide band gap, high current density, extensive operating temperature range, and high breakdown voltage [1] , [2] . The reliability and performance stability of GaN-HEMTs depend on the selection of the substrate and buffer layers influenced by the presence of defects and strain resulting from lattice mismatch. Thus, assessing device performance under various stimulations, such as bias and temperature acceleration, is essential to achieve reliable devices [3] . In this work, we examine the impact of PBTI on industry-standard power GaN MIS-HEMTs featuring two distinct buffer layers: AlN/AlGaN/GaN supper lattice (W1) and three steps graded AlGaN (W2), under positive-biased stress at V GS =20 V. PBTI tests reveal that W2 induced less Vth instability compared to W1 during positive bias stress. However, W1 demonstrates a faster recovery rate than W2, showing its superior robustness and more suitability for power switching applications.
