This paper discusses technological choices and resulting performances of an innovative Si/SiGe HBT architecture developed for a new 55-nm BiCMOS platform from STMicroelectronics targeting LEO satellites user terminals application in Ku-Ka bands. Transistor architecture has been designed to combine a low-noise performance with a cost-effective technology (for high-volume production), that are two major requirements for LEO satellite user terminals. Collector integration is widely simplified compared to previous BiCMOS technologies developed by STMicroelectronics taking advantage of ion implantation capabilities. Low-noise performance is addressed by a new generation of emitter-base architecture featuring an epitaxial base link, reducing the base resistance. Record noise performances are demonstrated with $NF_{\text{MIN}}\sim$ 0.6-dB at 20 GHz at device level and 1.13-dB at 11.85 GHz at circuit (packaged receiver) level associated to a gain of ~28dB. SiGe HBT also features −390 GHZ $f_\mathrm{T}$ and −500-GHz $f_\text{MAX}$

The high frequency and noise performance ( $T_{\mathrm {MIN}}$ , NF MIN , $R_{n}$ , and $Z_{\mathrm {sopt}}$ ) of SiGe heterojunction bipolar transistors (HBTs) are characterized for the first time from dc and $S$ -parameter measurements up to 70 GHz and from 2 to 400 K. Significantly improved current gain ~10 000, minimum noise temperature, $T_{\mathrm {MIN}}$ (< 1 K below 8.5 GHz), MAG, $f_{T}$ (458 GHz), and $f_{\mathrm {MAX}}$ (534 GHz) are observed at 2 K compared to 300 K, with no evidence of impurity deionization. It is found that the optimum noise figure current density, $J_{\mathrm {OPT}}$ , increases with temperature, following the crossover between shot noise and thermal noise. In contrast, the peak- $f_{T}$ and peak- $f_{\mathrm {MAX}}$ current densities increase by more than 50% at 2 K, likely due to the higher $v_{\mathrm {sat}}$ . A decrease in BV CEO , expected due to the higher current gain, and negative output conductance are observed in the 2–200 K range in the dc output characteristics at large currents above the peak- $f_{T}$ current.

This paper presents reliability assessment of basic integrated circuits designed for analog and RF applications based on extensive circuit simulations using the aging compact model, HiCuM-AL v3.0, dedicated to SiGe HBTs. The physic-based aging compact model implemented within HiCuM model is based on trap generation-annihilation mechanisms as well as the Fick hydrogen diffusion law. The model has been validated against results from HBT aging tests under various stress conditions followed by aging model parameter extraction. Due to its extensive use in integrated circuit blocks, different current mirror configurations subjected to mixed-mode stress conditions are studied and analyzed in order to quantify the impact of HC degradation on individual HBTs as well as on overall circuit performances.

A concise overview on the features of the most recently released version 3.0.0 of the industry standard compact bipolar transistor model HICUM/L2 is provided. The focus here is on the development of the model over the past ten years since its detailed description in [1]. The rationales for the various extensions, their physical background and some of the code implementation peculiarities are discussed.

This paper presents a new physics-based compact model implementation for interface state creation due to hot-carrier degradation in advanced SiGe HBTs. This model accounts for dynamic stress bias conditions through a combination of the solution of reaction-diffusion theory and Fick's law of diffusion. The model reflects transistor degradation in terms of base recombination current parameters of HiCuM compact model and its accuracy has been validated against results from long-term DC and dynamic aging tests performed close to the safe-operating-areas of various HBT technologies.

While 5G wireless networks are currently deployed around the world, preliminary research activities have begun to look beyond 5G and conceptualize 6G standard. Although it is envisioned that 6G may bring an unprecedent transformation of the wireless networks in comparison with previous generations, the necessity to develop analog and RF specialized technologies to address new frequency spectra will remain. In this paper, we review the development of PD-SOI CMOS and SiGe BiCMOS technologies addressing 5G RF Integrated Circuits (RFICs) and their evolutions for 6G.

In this paper, we present an in-situ thru-reflect-line (TRL) calibration and de-embedding kit that sets the reference plane in close proximity to the device under test. This is made possible thanks to the realization of the standards at the metal3 BEOL level, instead of the common meta1-8 solution. This novel calibration kit has been compared to classic TRL, both for parasitics assessment and by direct application on the active device (HBT) measurements.

This paper presents different de-embedding methods applied in semiconductor industry, used to retrieve intrinsic device performances from high frequency S-parameters On-wafer measurement. A de-embedding method with a reduced set of dummies is proposed for conducting accurate on-wafer device measurement in the gigahertz range. The experimental results on a device characteristic up to 110GHz show that it has a comparable accuracy than a more complex one.

The cut-off frequencies of silicon-germanium hetero-junction bipolar transistors (SiGe HBTs) have entered the THz range at the cost of high current density and relatively low breakdown voltages. Typically, the common-emitter breakdown voltage with open base (BVCEO) is used to indicate the allowed breakdown voltage related operation limit. However, an open base (i.e. an infinite source impedance) is rarely encountered in actual circuits, so that BVCEO may be exceeded to a certain extent, maximal up to the open-emitter breakdown voltage BVCBO. Therefore, compact HBT models need to be accurate beyond BVCEO up to BVCBO. In this paper, the enhancement of the avalanche current implemented in the latest version of HICUM/L2 is presented. The model has been validated for different types of advanced SiGe:C HBTs over a wide range of collector-base voltages and temperatures.

This paper deals with the reduction of the process thermal budget in a 55-nm BiCMOS technology for improving SiGe HBTs transit frequency, fT. Since MOSFETs are directly impacted by this modification, process adjustments are implemented to recover performances and parametric yield. Spike annealing temperature reduction, thermal re-oxidation replacement and Dynamic Surface Annealing implementation are discussed. A 355 GHz Ft/ FMax HBT compatible with current 55-nm MOSFET models is demonstrated.

In this paper we study and analyze the existing techniques in literature to extract the self-heating thermal resistance from the measured DC electrical behaviour of silicon-germanium heterojunction bipolar transistors (SiGe HBTs) focusing their dependence on device junction temperature and propose a simple extraction technique that shows superior accuracy than the existing extraction methodologies. Our approach is scalable and validated with model card simulations across different emitter geometries for a wide temperature range. We also present the applicability of our approach on measured data of a SiGe HBT fabricated in STMicroelectronics B55 process.

This paper presents a novel Fully Self-Aligned (FSA) Si/SiGe HBT architecture using Selective Epitaxial Growth (SEG) and featuring an Epitaxial eXtrinsic Base Isolated from the Collector (EXBIC). The one is integrated into the bulk area of the 28-nm FD-SOI CMOS technology developed at STMicroelectronics. All the parameters of the architecture such as the boron-doped base link, the emitter width and height, the pedestal oxide and sidewall thicknesses are evaluated by TCAD simulation. A low base-collector capacitance, independent from the extrinsic base doping is obtained. Optimized architecture exhibits 420 GHz f T and 780 GHz f MAX .

This paper presents and discusses the challenges and solutions to calibrate the TCAD of high-speed DPSA-SEG Si/SiGe HBTs in 55-nm BiCMOS. The variation of the 1D doping profiles with the emitter width observed from EDX measurements has been addressed by TCAD simulation. Simplified base link formation by controlling the boron diffusion through polycrystalline / mono-crystalline interface in Sprocess simulation is a central step to capture a reasonable maximum oscillation frequency (f MAX). Finally all physical models including band-gap narrowing, saturation velocity, high-field mobility and SRH recombination, which impact the SiGe:C HBTs performance, are calibrated in Sdevice module of Synopsys®.

In this paper we demonstrate a new and simple approach to obtain isothermal electrical characteristics of metal oxide field effect transistor (MOSFET) from conventional non-isothermal measurements. DC and continuous wave (CW) S-parameter measurements are performed at different chuck temperatures (Tchuck). Knowing the thermal resistance (RTH) of the device the variation of DC and AC characteristic due to self-heating can be de-embedded and all the isothermal DC data and AC data above isothermal frequency can be determined. The method is validated by comparing the results with pulsed DC and pulsed RF measurements and found to be in good agreements.

The objective of this paper is to predict the main electrical characteristics of SiGe NPN HBTs, like the transit frequency fT, internal capacitances and pinched base sheet resistance for the next CMOS nodes by means of process and hydrodynamic simulations. The as-deposited BiCMOS055 vertical doping profile is exposed to the thermal budgets from existing CMOS040, CMOS028, CMOS028FDSOI and CMOS014FDSOI technologies by TCAD simulation. Obtained results show that, thanks to the reduction of the process thermal budget, the maximum fT could reach 370 GHz with two different assumptions: identical doping level at both BE and BC junctions and identical BE capacitance. Additionally, the evolution of the dopants' diffusion with ST's fabrication steps is clarified for BiCMOS055 in this study.

•A methodology to obtain isothermal electrical characteristics of MOSFET.•Applied on conventional non-isothermal DC and CW S-parameter characteristics.•Characterization on 28nm bulk CMOS technology at different ambient temperature.•Validated of isothermal data through pulsed DC and pulsed RF measurements.

A new and simple approach for nonlinear modelling of the dynamic self-heating effect in bulk complementary metal–oxide semiconductor (CMOS) field effect transistors is presented. Low-frequency S-parameter measurements are performed in 28 nm bulk CMOS technology at room temperature between a 10 kHz and 3 GHz frequency range and the thermal impedance (Z TH) of the devices is extracted. The proposed model is validated through the measurements for different bias points. The results obtained demonstrate a reasonable agreement between theoretical prediction and experimental data.