We report on a novel radiation hardening by design (RHBD) approach for mitigation of total ionization dose (TID) induced drain leakage currents and single event transient (SET) in digital circuits fabricated in a 130 nm bulk SiGe BiCMOS technology. In order to avoid significant TID induced increase of drain leakage currents for NMOS transistors and channel pinch-off for PMOS transistors due to positive charges trapped at the lateral shallow trench insulator silicon interface we introduced junction isolation (JI) for the lateral MOS channel regions. The device construction measures applied also support to suppress the generation SETs. The tolerance of JI MOS transistors against TID induced drain leakage currents was verified up to a TID > 1.3 Mrad(Si). SET tests performed at four different inverter types varying in the arrangement the deep well in the layout. For CMOS inverters with isolated NMOS transistors a LET threshold > 130 MeV cm(2) mg(-1) was obtained.

Mixed signal on-chip solutions for space applications and high energy physics experiments require high voltage RF-LDMOS transistors with sufficient ruggedness against ionizing radiation and single event burnout. We report on a novel hardening by design approach for radiation tolerant integrated RF NLDMOS transistors confirmed by single event burn out (SEB) and total ionizing dose (TID) radiation tests. In order to substantially decrease TID induced leakage currents the shallow trench isolation (STI) of MOS transistors was replaced by narrow junction isolated regions. For a significant increase of the SEB onset voltage a cascode arrangement consisting of an isolated NMOS and NLDMOS was chosen. The floating NMOS-drain/NLDMOS-source node in the cascode arrangement is always reverse biased which efficiently avoids a turn-on of the parasitic npn bipolar transistor. The rad-hard isolated NMOS/NLDMOS cascode features a breakdown voltage BVDS > 50 V, a maximum cut off frequency fT = 5 GHz and a maximum oscillation frequency fMAX = 14 GHz. In comparison with standard NLDMOS transistors the isolated NMOS/NLDMOS cascode device shows an increase of the SEB onset voltage from 14V to 30V at a linear energy transfer LET of 67.7 MeVcm2/mg and a negligible increase of source drain leakage currents up to a TID of 1.5 Mrad after irradiation with a 60Co source.

In order to improve the total ionizing dose (TID) and single event upset (SEU) radiation tolerance of bulk CMOS technologies we applied two constructive measures. TID induced source-drain leakage is suppressed by a junction isolation (JI) of the source drain regions using silicide blocked well regions. To decrease the susceptibility against SEU we introduced a redundancy on transistor level, where each MOS transistor is replaced by a stack of two spatially separated single transistors which share a common gate (CG). The radiation hardness and device performance of the novel JICG MOS transistors fabricated in IHP's 250 nm SGB25RH technology were evaluated.

We have investigated the ionization damage by 60 Co gamma irradiation in 0.13- and 0.25- $\mu \text{m}$ SiGe heterojunction bipolar transistors (HBTs). Both technologies feature high-speed HBTs (HS-HBTs) together with high-voltage HBTs (HV-HBTs). Base current degradation with increasing total irradiation dose is studied. An identical behavior of corresponding HS-HBT and HV-HBT is found for operation in forward mode probing the emitter–base junction. In reverse mode where the collector base junction is determining the base current degradation, HV devices exhibit larger degradation than their HS counterparts. The increased width of the collector–base space charge region in HV devices leads to enhanced interface recombination at the adjacent Si/oxide interfaces and stronger base current degradation. TCAD simulations of device degradation suggest a linear relationship between total irradiation dose and radiation-induced interface state density $N_{\mathrm{ it}}$ .

The operation of SiGe HBTs at cryogenic temperatures is investigated experimentally and theoretically. It is demonstrated that the collector current at cryogenic temperatures is caused by electron tunneling through the base. The temperature dependence of the transistor characteristics reveals a transition from conventional thermally activated transport at room temperature to tunneling dominated transport at cryogenic temperatures. Experimental results are presented for HBTs with a peak current gain of 8000 at 300 K and 45000 at 10 K.

Mixed signal on chip solutions for space applications and high energy physics experiments require high voltage RF-LDMOS transistors with a sufficient ruggedness against ionizing radiation and single event burn out effects. We report on the effectiveness of a novel hardening by design approach for radiation tolerant integrated RF power MOSFET transistors confirmed by single event burn out (SEB) and total ionizing dose (TID) radiation tests. In order to substantially decrease the TID related leakage currents the lateral shallow trench isolation (STI) was replaced by narrow junction isolation regions. To significantly increase the onset voltage for SEB events of LDMOS transistors a MOS/LDMOS cascode arrangement has proven as a suitable approach. The common floating MOS drain/LDMOS source node of the cascode arrangement is permanently reverse biased, so that the turning on of the LDMOS parasitic bipolar transistor is suppressed. The properties of the Junction Isolated Cascode LDMOS with respect to area consumption, DC and RF performance and ruggedness against malfunctions due to TID and SEB effects were verified by comparison with standard trench isolated NLDMOS and junction isolated NLDMOS devices. The junction isolated NMOS/NLDMOS Cascode features a break down voltage BVDS > 40V a maximum cut off frequency f T =15 GHz and a maximum oscillation frequency f MAX = 25 GHz. In comparison with standard NLDMOS the laterally junction isolated NMOS/NLDMOS Cascode device shows an increase of the SEB onset voltage from 14V to 24V at a linear energy transfer LET of 67.7 MeVcm 2 /mg and negligible source drain leakage currents up to a TID of 1.5 Mrad after irradiation with a 60Co source.

An experimental SiGe HBT technology featuring fT/fmax/BVCEO = 505 GHz/720 GHz/1.6 V and a minimum CML ring oscillator gate delay of 1.34 ps is presented. The improved speed compared to our previous SiGe HBT developments originates primarily from an optimized vertical profile, an additional decrease of the base and emitter resistance which is made possible by combining millisecond annealing with a low-temperature backend, and from lateral device scaling.

An experimental SiGe HBT technology featuring f(T)/f(max)/BVCEO = 505 GHz/720 GHz/1.6 V and a minimum CIVIL ring oscillator gate delay of 1.34 ps is presented. The improved speed compared to our previous SiGe HBT developments originates primarily from an optimized vertical profile, an additional decrease of the base and emitter resistance which is made possible by combining millisecond annealing with a low-temperature backend, and from lateral device scaling.

Applications such as radar imaging and wideband communications are driving the research on millimeter-wave circuits. For some applications SiGe hetero junction bipolar transistors (HBTs) are limited in output power. III-V technologies (like InP) can realize devices showing a high product of peak transit frequency multiplied with the open base breakdown voltage. Therefore, merging the qualities of both III-V and Si technology will enable a new class of high-performance ICs. Our approach combines an InP-DHBT transferred-substrate process with a Si-BiCMOS process. The key method is an aligned face-to-face wafer bonding with a subsequent removal of the InP substrate. Different integrated signal sources with an output frequency up to 246 GHz were designed and produced using different combinations of BiCMOS and InP circuit building blocks to demonstrate the capabilities of the hetero-integration routine. In this paper the influences of the wafer bonding and the finalization of the InP-DHBT process on SiGe devices were investigated. It was found that the influences on the BiCMOS devices were rather small.

Isolated LDMOS transistors with thin gate oxides and good RF performance are key components in integrated RF circuits where large voltage shifts are required for the circuit functionality. We demonstrate the modular integration of isolated NLDMOS and PLDMOS focusing on maximal RF performance into an advanced industrial 0.25 μm SiGe:C BICMOS process. A boundary condition for device construction was a limit for maximum deep n-well implantation energy of 750keV. The achieved values BVDSS/fT/fMAX of -21V/10GHz/35GHz for the PLDMOS and 16V/30GHz/53GHz for the isolated NLDMOS, respectively, reflect the excellent RF performance obtained.

A 0.13 µm SiGe BiCMOS technology for millimeter wave applications is presented. This technology features high-speed HBTs (fT=240 GHz, fmax=330 GHz, BVCEO=1.7 V) along with high-voltage HBTs (fT=50 GHz, fmax=130 GHz, BVCEO=3.7 V) integrated in a dual-gate, triple-well RF-CMOS process. Ring oscillator gate delays of 2.9 ps, low-noise amplifiers for 122 GHz, and LC oscillators for frequencies above 200 GHz are demonstrated.

A 0.13 μm SiGe BiCMOS technology for millimeter-wave applications is presented. This technology features high-speed HBTs with peak transit frequencies fT of 240 GHz, maximum oscillation frequencies fmax of 330 GHz, and breakdown voltages BVCEO of 1.7 V along with high-voltage HBTs (fT = 50 GHz,fmax = 130 GHz, BVCEO = 3.7 V) integrated in a dual gate oxide RF-CMOS process. Ring oscillator gate delays of 2.9 ps, low-noise amplifiers for 122 GHz, and LC oscillators with fundamental-mode oscillation frequencies above 200 GHz are demonstrated.

The integration of RF NLDMOS transistors into a 0.13 μm CMOS process for operating at X-Band (8.5-10.5 GHz) frequencies with over 11 dB gain and 0.25 W/mm power density and 22% power added efficiency at 1 dB output power compression is presented. The self aligned NLDMOS was modularly integrated into IHP's 130 nm SiGeC BiCMOS platform targeting 1 W X-Band power amplifiers for radar and satellite communication applications.

A SiGe HBT technology featuring f T /f max /BV CEO =300GHz/500GHz/1.6V and a minimum CML ring oscillator gate delay of 2.0 ps is presented. The speed-improvement compared to our previous SiGe HBT generations originates from lateral device scaling, a reduced thermal budget, and changes of the emitter and base composition, of the salicide resistance as well as of the low-doped collector formation.