Advance of knowledge in material engineering has introduced stretchable electronic materials which can be stretched, bended or twisted and it is beneficial for consumer product manufacturing. This paper aims to study the effect of process combination of standard printing process in surface mount technology and thermoforming process on a stretchable conductive polymer to form a 3-dimensional electronic device. The polymer comprised of silver particles as fillers was prepared to produce a conductive and stretchable behavior which can withstand high temperature deformation. It was printed on a flat substrate using a screen printing technique and then being thermoformed to produce 3-dimensional shape of automotive rear lighting. Mechanical and electrical performances of the thermoformed product were characterized before and after thermoforming process to study the reliability of LEDs assembly with stretchable circuits. Four point probes instrument was used to measure resistivity of the printed circuit which was elongated due to thermoforming process. The elongation of circuit varied throughout the lighting prototype depending on complex geometry of mould. Conductivity of the circuit was also tested by LEDs illumination. Results of microscopy investigation, x-ray imaging and thermal cycling show good performances of LEDs joints. This new manufacturing process of printed circuit offers a promising future alternative method in manufacturing of 3-dimensional electronic device.
In wire bonding process, one of the key factors to have a good bonding quality is the cleanliness of the bonding surfaces whether it is bonding pad (Die) or lead (leadframe). Foreign particles, contaminations, discolorations on bonding surfaces are common causes of non-sticking of ball bond. Improving material handling procedures, cleanroom procedures, additional line processes, improvement in process controls, process parameter optimizations, etc. are some of the preventions and improvement actions being carried out by semiconductor companies to minimize or eliminate such bonding surface conditions. In this paper, improvement of Non-Sticking On Pad (NSOP) caused by impurities or contaminations formed after ArH2 plasma cleaning process will be shown. It is detected in the impacted bonding pad surface a thick layer of "O" underneath the "C" layer when undergo depth profiling using X-ray Photoelectron Spectroscopy (XPS) surface analysis. Wirebond 1st bond parameter have been optimized to break through these "O" layer which is believed to be a film of hydroxyl (-OH) where one hydrogen atom combined to one oxygen atom formed after the ArH2 plasma cleaning process. The wirebond parameter (pre-US power) used in this non-sticking on bond pad improvement is not new in the wirebond equipment available today in the market. But with its function, ball bonding was able to break through the thick "O" layer and good bonding is achieved.
In recent years, flip chip packaging by application of a copper pillar bump as an interconnector within the packages has successfully shrunk the package size to a minimum level, by maintaining or maximizing the chip application functionality. Nevertheless, some weaknesses have been observed during the formation of solder joint connection between the copper pillars to die pad substrates. The most common defect, which is solder void formation at the solder joint area, will reduce the interconnection strength or robustness of the solder joint. To understand the solder void formation mechanism, a simulation experiment has been carried out by using copper and silver plated lead pad substrate for pillar solder joint formation process at different stress time interval. An analytical analysis by using 3D CT-scan has been carried out to detect the submicron size solder void defect, especially during high-temperature stress process. An elemental analysis by energy dispersive X-ray also has been carrying out to prove the substrate pad material dissolution mechanism during solder joint formation. With the experiment finding and deeply understanding the material dissolution behavior in packaging concept, this can ensure more robust pillar joint die bond process and guarantee quality packages built.
The amount of electronics within vehicles continue to increase with the drive towards autonomous driving and green vehicles through improved engine controls and hybrid or full electric vehicles. Engine control units require electronic components which are located very close to the engine, and thus must operate within a high temperature ambient environment, at least meeting AEC Grade 1 or Grade 0 requirements. This paper reviews the bill of material selection for quad-flat package (QFP), in particularly, mold compound and copper wire, with high density leadframes. Palladium coated copper wire (PCC) is the current preferred wire of choice due to the improved manufacturability. Although PCC wire is susceptible to galvanic corrosion due to the presence of sulfur in the molding compound, the level of corrosion is minimal and impact is cosmetic only. Wire sweep is a major factor in the mold compound selection, especially for high density leadframes. Wire sweep percentage differs greatly from row to row, and mold compound type contributes significantly for a robust process on high density leadframes. Furthermore, on large body sized QFPs, package warpage is another main consideration in the selection of mold compound type as warpage directly impacts the lead co-planarity. It is shown that additional heat treatment post assembly, such as during burn-in, may contribute significantly towards warpage degradation. As such, it is necessary to select the molding compound with sufficiently low warpage through repeated heat treatment on the package. Lastly, the selected mold compound needs to meet the delamination requirements as per AEC-Q006 for copper wire interconnects.
Saw singulation is an indispensable process to singulate the Micro Carrier Device (MCD) strips into individual units in assembling Quad Flat No-lead (QFN) packages. Mechanical saw, cutting the MCD strip along saw streets using dicing blade, is a mainstream mode in the saw singulation process. The growing variety and complexity of leadless packages present a true challenge to Back-End processes. Recent customer demand for a lead with side solder-able or wet-able pocket to ease their AOI has led to new challenges for conventional blade and dicing process. Due to this reason, this paper will reveal the challenges in singulation process to meet customer requirement over corner wet-able pocket design. All the activities towards burr-removal process on the corner lead involving process and method optimization through conventional sawing and advanced dicing method will be shared in this paper. Process and method optimization via mechanical dicing involving various blade selection, additional cut channel, different cut method and direction only able to minimize the occurrence of the burr but not eliminate the symptom. As part of the recommendation for future works, an advanced approach in dicing technology, namely laser singulation and water jet was proposed to mitigate the risk of burr on wet-able pocket. On one hand laser dicing showed better response over burr removal but on other hand pose a risk of laser ablation mark on EMC surface. In addition, suitable laser method selection is important to ensure the best performance. Finally, by performing water jet in between the singulation process, significant results were achieved with an improved and way better dicing responses and cutting quality-burr. Water jet pressure of max 600Bar and conveyor speed max 2m/min in combination with half cut mechanical sawing process found to be able to meet the expectation.
Over the years, power semiconductor package evolved from normal density lead frame design to high density lead frame design. To catch up the package cost reduction while maintaining its manufacturing quality, tooling design related to lead frame stamping tool and molding tool become more challenging to semiconductor industry. The mismatch between lead frame and mold tool makers' capability has continuously impact to the unit package with various quality incidents; such as pinch copper (lead burr), package offset and etc. To overcome the quality impact, the manufacturing capability of lead frame supplier and mold tool maker has been pushed to the limit. In this paper, the pinch copper (lead burr) study has been done on the delta assessment between lead frame and mold tool capability limitation such as dimension and tolerances. Both lead frame and mold tool have manufacturing tolerance constraints in order for the package to be free from pinch copper and side lead mold flash occurrence. To understand the manufacturing tolerance capabilities, the measurement method on the mold tooling as well as lead frame has been studied and demonstrated prior to any solution imposed. In addition, dimensions and tolerances were identified and defined based on the coefficient of expansion (CTE) matching between lead frame and mold tool material. Based on the CTE chart, the minimum delta tolerance that is allowed between the two materials was illustrated. After confirming the minimum delta tolerance, this is converted into controllable dimension for both lead frame and mold cavity anti flash. Mold cavity positioning and antiflash dimension has been optimized. New lead frame sample with new control dimension has been manufactured for a feasibility assessment. The feasibility sample showed positive results on pinch copper and side lead mold flash elimination after following the newly defined control dimension. The result was further validated with high volume manufacturing run.
Reliability defects associated with thermal humidity environments are not new to the electronics packaging industry, yet to this day it remains a key concern even for our latest technologies. Moisture absorbed into electronic packaging can impact package warpage, cause corrosion, underfill crack and interfacial delamination. Fundamental studies are needed to better understand the effect of moisture interaction with different package designs. This paper summarizes the lab experiments and Finite Element Analysis (FEA) that have been performed to study package moisture absorption-desorption, room temperature (RT) warpage and dynamic warpage, on packages post exposure to thermal humidity environment. This has yielded good fundamental learning and identified areas for future work.
Sintered silver (Ag) is being used as a Pb-free die-attach material for selected high-temperature application. Reliable sintered Ag joint depends on sintering pressure, time, temperature, paste formulation, bonding area and environment to achieve the desired density and bonding to the substrates. Interfacial region determines the bonding strength as much as the densification of the sintered Ag joint. Air atmosphere sintering of micron-Ag paste oxidized the Cu substrate to prevent any inter-diffusion of Ag atoms which were observable under HR-TEM. Yet, these copper oxides acted as adhesive to produce higher die shear strength than those sintered in the forming gas (N 2 -5%H 2 ). The N 2 -5%H 2 environment assisted the densification and sintering of micron-Ag to the pristine Cu substrate; increasing the bonding quality and die-shear strength, compared to the total absence of bonding for the micron-Ag paste sintered in N2 environment. This result highlights the importance of using high resolution TEM to understand the strengthening mechanism of micron-Ag joints at Cu substrates in air and forming (N 2 -5%H 2 ) gases environment.
Scanning acoustic microcopy (SAM) method with inverted inspection direction has been successfully develop and evaluate the quality of flip chip underfill and interconnect bonds in manufacturing of microelectronic components. Acoustic microscopes utilize high frequency ultrasound transmitting through the silicon chip backside in one scan to access and examine the internal structures in optically opaque materials. These non-destructive methods relatively enable the defect localization which leads microstructural examinations involving destructive analysis sample preparation. For the justification of accuracy of SAM method analysis, a destructive cross-sectioned and mechanical lapping physical analysis were performed for preparing the samples and examine by optical microscope and Scanning Electron Microscope (SEM) for defect verification. Cases studies have been demonstrated that the capabilities of conventional SAM inspection and advantages over other analysis method.
Power Metal Oxide Semiconductor Field Effect Transistor (MOSFET) die thickness is getting thinner over time due to improvement of power efficiency in new advance power electronic packages. This has caused solder voids performance deteriorates as the result of die warping after thinning and caused die crack issue. Vacuum reflow is introduced to improve that solder void issue with the target of 5% or below from origin 20%. During the study, die pop challenge was encountered at vacuum reflow process. In this paper, the root cause and solutions of the die pop will be discussed. The challenge of this project is to achieve zero die pop defect while meeting 5% or below solder void sizes underneath warped die in high productivity mode condition. A thorough pressure profile optimization was conducted in meeting these requirements that always in contradiction between die pop and low void in limited vacuumed time condition at vacuum pressure profile. Optimizing vacuum pressure level with two steps profile and solder paste deposition volume are critical in achieving the goals.
Gen2 Taper is built by Infineon Technologies THA department which is used for taping the component into ammopack packing. Gen2 taper is running 100% volume of PG-SSO-2-53 in PSSO STS line. The topic was self-initiated by team looking at the poor performance of Gen2 Taper with OEE 52.5% (Target 75%) and Yield 96.43% (Target 97.60%). The poor yield performance is the main detractor that caused overall PSSO STS unable to achieve the TCR (Target Cost Roadmap) target. It had been a bottleneck process deciding the delivery quality to the customers. The initiative above has got very positive management buy-in as this would avoid poor delivery which upset the customers. Harvesting the project will directly contributed to NLoP (Next Level of Productivity) because of better delivery, better yield.
Seremban QFN line has enjoyed continuous growth of production volume for Multi-die Driver/Controller MOSFET (DrMOS) package. Current production DrMOS device integrates a Driver/Controller, high-side MOSFET and low-side MOSFET into a 6 mm × 6 mm 40-pin QFN packaging. To be able to continue our fair share on the market though, new package and new case outline which comes into a 5 mm × 5 mm QFN32 project was recently developed for production. The new package consists of a FET die, Copper Clip and Controller die which are stacked to reduce the overall solution size. This paper elaborates specifically the wire bond challenges and corresponding improvements executed addressing the issues, hence making this package the reference for subsequent DrMOS with Stacked Controller Die on Copper Clip. To be able to define the allowable maximum loop height that can consistently meet the minimum stacked Controller die to Top Package clearance and marking depth requirements, package stack-up worst case analysis and loop height robustness study that can meet up to +6 sigma were evaluated. Since the Controller die is sitting on top of the FET die and Copper Clip, simulation on worst Controller die displacement scenario from different directions was also assessed to guarantee enough bonding wire to Copper Clip edge clearance. Reliability, bondability, wire bonding parameters characterization and cliff experiments were studied as well to ensure critical responses are well within pre-defined specification after implementation of new package design.
The introduction of new package to accommodate Power silicon technologies with die sizes ranging from a minimum A mm2 to the maximum B mm2 with gullwing feature introduced new challenge to Al 500um wire size as the clearance between the highest looping wire to the top package becomes narrower and critical. The downset dimension of the new package reduced by 41% (from 760 um to 350um with reference to existing package) leaving the looping clearance now only 1000um from previously 1400um for Al 500um wire to have an ample space for looping founation (measure from the lead post). This will cause a new challenge to be proven for looping founation as it becomes critical. Initial feasibility study shows an evidence of expose wire from the molding compound on new package and package stack analysis also revealed potential of having exposed wire in ppm level. Looping optimization for single stitch has been conducted and able to perfoun a stable looping founation within the 1000um clearance for Al 500um wire. A new specification for the maximum looping has been implemented to ensure all the readings for maximum wire loop heights are under production control. This paper describes in details the looping optimization and the actual capability demonstrated for Al 500um wire to enable the project to be released for production without any issue in the project qualifications and production released in Dec 2017. The new looing capability for stable production has been demonstrated for such a low loop (< 800um) with critical looping clearance (within 1000um) for Al 500um wire and passed the Automotive requirements. This perfounance will enhance to enable another new package platfoun to be introduced in the semiconductor industry with Top Side Cooling capability which currently under feasibility stage.
Formation of Pb (Lead) flakes after die attach reflow process is a common concern when soldering packages with high temperature and soldering material with high in Lead components. Pb flakes are visually manifested on the chip bonding pad after the post Reflow cleaning process, general term as "flux cleaning process". Small Pb solder spheres can leave behind stains on bonding pad and could reduce wire-bonding yields, with the failure mode of non-stick-on-pad. This Pb flakes formation was investigated and the findings from this phenomenon will be discussed in this paper since very few studies found in current literature. Hypothesis for Pb flakes formation could be attributed during solder Reflow process. Rapid temperature excursions caused the flux component within the solder paste to rapidly expand. Some of the ingredients within the flux component will reach their boiling temperature, at which small solder spheres will experience "popcorn effect" and re-deposited themselves to the bond pad. Hence, this paper also described the feasibility studies of different flux cleaning methods on how to effectively remove this Pb flakes. Process/ Equipment and Materials were considered on these studies to validate the applicable solutions for Pb flakes removal on bonding pad. Considerations are the following for the flux cleaning evaluations; Equipment: Spray-in-Air (Water-based chemical), Centrifugal type (both Water-based & Solvent-based chemicals) and Ultrasonic (both Water-based & Solvent-based chemicals). Due to implications or risks identified from these feasibility considerations, the current Ultrasonic process + new cleaning Chemistry with better results were selected to precede further evaluation, including Reliability assessment.
Lifted wedge on lead has been the common defect mode (as in Figure 1) encountered in wire bonding process. There are numerous causes for lifted wedge in which many have more obvious causes and some are more eluded to be identified and resolved. This article elaborates on the root causes of lifted stitch, like characterization of a good clamping design and layout through multiple output responses such as bonder current curve traces, design layout simulation, bending test and the shorter foot wedge tool bond parameter through DOE. This solution proved able to eliminate the lifted wedge problem.
Development of mircoelectronic packages are always moving towards smaller and thinner. This is in conjunction of consumers need for mobile and wearable electronic gadgets. In order to achieve this, beside improvements in packaging technologies silicon die had to be smaller and thinner too. However thinner packages increase the challenges of package stress and thinner silicon chip becomes more susceptible to process related weakness especially at the front-end processes. Silicon die strength is an important parameter to ensure the packing reliability under stringent conditions. The strength of silicon wafer is heavily influenced by the die thickness and wafer the backside surface preparation prior to metal deposition. Stresses induced in the silicon die throughout the process of wafer processing, packaging and die assembly. Small flaws such as small micro cracks or uneveness can occur during backside processes causing the strength of the Silicon die to decrease and cause failure at early stage of packaging process or even reliability concern. This paper investigated the effect of die strength to the surface morphology using 3 point bending test and 3D Laser Measuring Microscope. The die strength was characterized using 3 point bending test while surface morphology was characterized using 3D Laser Measuring Microscope. The evaluation was performed with silicon die singulated from wafers of unevenness at wafer backside. The silicon die was then categorized into 4 different types by unevenness location, 1) unevenness through complete die in x-direction, 2) unevenness through complete die in y-direction 3) unevenness at the middle of die, 4) unevenness at the edge of die. Silicon die strength of 4 different type of location of unevenness was being measured using 3 point bending test. The result showed that the depth of unevenness was not the main factor of low die strength. Unevenness location at the die is the main factor of low die strength. Die strength with unevenness at the edge of die having the lowest strength.
This paper introduces a package defect test system known as “Capacitive Testing” setup in assembly manufacturing. Using In-Circuit Test (ICT) design concept from mother board testing was made possible to enhance I C testing by doing package defect testing in the semiconductor industry. It provides simplified open/short test features and added with built-in test feature to detect package structural related defect. Primary focus on such a critical package defect known as “near-short” condition occurring between neighbouring wires and/or inner leads. This kind of defect is known not able to screen out by x-ray inspection and Automatic Test Equipment testing (ATE). At present., this package defect tester application already running full scale and gained significant results in Quality aspect with zero customer complaints ever since implemented in assembly production. The tester performance had been improved its capacity to achieve productivity improvement with higher OEE%, reduce number of low yield lots with high final test yield and contribute high cost avoidance of assembly spill. This package defect tester can be further benefits to entire customer by cascading in testing wide range of packages in semiconductor industry.
Semiconductor packaging's solder void criteria is getting tighter overtime due to involvement of high usage in automotive industry. Semiconductor packaging component maker starts to strengthen the solder joint quality and electrical power conductivity by tighten the solder void requirement through seeking a solution in controlling the maximum solder void size reduction from 10-15% original fraction to 5% or below over die size. Vacuum reflow is introduced to overcome this challenge. Critical process parameters in vacuum reflow process including temperature and pressure were characterized for void reduction and compared to that of conventional reflow process. Promising results show that high temperature, fast depressurize rate and long pressure dwell time in low pressurized environment as well as solder paste volume increment are critical factors in providing minimum solder void sizes that successfully meet the new industry criteria.
Electroless Nickel Immersion Gold (ENIG) plating could offer superior durability and high corrosion resistance as well as providing excellent solderability. However, in plating chemistry field, poor intermetallic between 2 metals will lead to adhesion failure, and which would impact customer mounting application or even field failures. The main challenges to achieved robust manufacturing process is to understand adhesion failure mode between Nickel (Ni bump) to Nickel Phosphorous (Ni-P), based on several factors. A fundamental aspect underlying the coating process can be defined in bath technique, parameter and pre-process preparation. In this study, author investigating on previous series of improvement actions in adhesion failure. Based on lesson learn, all implemented action done with assumption that individual quality indices are independent to each other. But in real practise, the assumption may not be valid always. A Series of Block RSM were performed to verified current control in TSxP Galvanic Manufacturing line. Introduction of outlier parameter in the DOE is to increase the experiment window, and adhesion test act as output response (C=0). Then, developed mathematical model from RSM regression were used to validated and analysed the develop model with current production window (loading factor). From RSM analysis, “ZERO” adhesion failure event can be achieved via optimization of current production window (loading factor).
