This paper presents a high-efficiency wideband GaN-HEMT power amplifier (PA) employing a novel three-path multi-harmonics-controlled impedance matching network for broadband harmonic regulation and enhanced output performance. The proposed architecture integrates a three-path output matching topology with a harmonic-regulating bias network to simultaneously control fundamental, even-order, and odd-order harmonics across multiple frequency points. In addition, the matching structure acts as a buffer stage, reducing signal reflections and improving impedance transformation over a wide operating bandwidth. To validate the proposed approach, a 25-W GaN HEMT PA using the CGH40025F device is designed, fabricated, and experimentally characterized over the 2-4 GHz frequency range. The fabricated prototype achieves a fractional bandwidth of 67%, with a measured drain efficiency of 54-65%, power-added efficiency of 47-52%, saturated output power of 43.1-44.6 dBm, and large-signal gain of 7.1-9.5 dB. Furthermore, the proposed PA demonstrates good linearity and stable harmonic suppression across the full S-band. The measured results confirm that the proposed multi-harmonics-controlled matching topology provides an effective solution for realizing high-efficiency, high-power, and wideband GaN microwave power amplifiers suitable for modern wireless, radar, and microwave communication systems.
Instrumentation amplifiers (INAs) are essential building blocks in biomedical and precision sensing applications, where high gain, strong common-mode rejection ratio (CMRR), and low power consumption are required. This study proposes a structured approach for designing highly accurate CMOS INAs intended for bio-potential measurement applications, including signals like electrocardiogram (ECG), electromyogram (EMG), and electroencephalogram (EEG). The design process begins with the implementation and evaluation of three two-stage CMOS operational amplifiers (Op-Amps) that are telescopic (TS), cascoded differential input (CDI), and dual transistor differential input (DTDI) in 180 nm CMOS technology. The three Op-Amp designs achieve differential gains of 80.93 dB, 67.20 dB, and 63.02 dB; CMRR values of 151.8 dB, 125 dB, and 107.9 dB; unity-gain frequencies of 36 MHz, 60 MHz, and 35 MHz; phase margins of 88°, 80°, and 92°; slew rates of 27.54 V/μs, 14.95 V/μs, and 70.97 V/μs; and power consumptions of 225.18 μW, 143.51 μW, and 126.73 μW, respectively. These three Op-Amps are then used to construct nine CMOS INAs: three identical INAs (each built using the same Op-Amp topology) and six hybrid INAs combining different Op-Amp architectures. All designs are simulated under identical process, voltage, temperature, and loading conditions to ensure a fair comparison. The resulting INAs achieve differential gains up to 119.76 dB and CMRR values ranging from 83.7 dB to 111.5 dB, without requiring chopper stabilization or bipolar processes. Among the hybrid architectures, the CDI–TS INA demonstrates the most balanced performance for biomedical signal acquisition, providing high gain (118.6 dB), strong CMRR (110.3 dB), stable phase margin, and moderate power consumption (529 μW). The DTDI–TS INA offers a lower-power alternative with comparable gain and CMRR characteristics. These results highlight the effectiveness of hybrid Op-Amp combinations for amplifying low-amplitude bio-signals and enabling precision sensor interfaces.
Approximate multipliers are important building blocks for energy-efficient artificial intelligence (AI) hardware. This paper proposes two fast high-order approximate compressors, AC5-2 and AC6-2, derived through Karnaugh-map-based logic simplification. These compressors directly reduce five or six partial products to two outputs with low logic complexity, while satisfying non-positive-error and zero-preserving constraints. Using these compressors, we construct two 8-bit unsigned approximate multipliers, LPAM1 and LPAM2, employing linear and broken-line hybrid compression strategies. Experimental results in the SMIC 55-nm process show that, among the evaluated recent approximate multipliers, LPAM1 achieves the smallest area and power. It reduces multiplier-level dynamic power by over 81% compared with the exact multiplier, while causing only a Top-1 accuracy decrease of 0.20 percentage points on ResNet-18/ImageNet. LPAM2 provides improved error metrics with slightly higher power. Both multipliers preserve the zero-input condition and maintain high image quality (PSNR > 49 dB) in visual tasks. These results demonstrate that the proposed high-order compression architectures provide favorable hardware–accuracy trade-offs for error-tolerant intelligent computing.
Matrix inversion is a computationally complex operation used in numerous scientific and engineering domains, from signal reconstruction to control systems. One such application is the Least Squares (LS) problem in Orthogonal Matching Pursuit (OMP), a Compressive Sensing (CS) reconstruction algorithm. Matrix inversion can be performed through QR decomposition (QRD) or the Gaussian Elimination (GE) method. This study investigates the performance of different factorisation algorithms and their effectiveness through High-Level Synthesis (HLS). Through directive-based loop and control optimisations in HLS, the study evaluates latency, resource usage, and throughput. The investigations for both fixed and floating type representation, for different matrix sizes, are reported on a Zynq xc7z020-clg484-1 FPGA device. The optimized floating-point implementation achieves 8.8% higher operating frequency, 67% lower latency, approximately three times higher throughput, and 75% lower numerical error than the fixed-point implementation, while the fixed-point implementation significantly reduces hardware resource utilization, making both implementations suitable for compressive sensing applications with different performance and resource requirements. The optimized Modified Gram-Schmidt (MGS) method and Incremental GE method have better execution time and resource utilization as compared to other classical methods in previous studies, amidst trade-offs. The optimized inversion techniques apply to wireless communications and signal processing applications where resource constraints and precision trade-offs are critical.
