We demonstrate a fabricated stateless RISC-V optical intermittent platform integrating photovoltaic harvesting, supercapacitor buffering, PMU-gated power management, and a UART-programmable RISC-V core. By replacing fixed-function sensing/control logic with a small software-programmable CPU, the platform supports more flexible on-node processing under harvested intermittent power without requiring checkpointing or state-retention hardware. After each interruption, the system restarts from a known boot state. Because the platform is powered directly by an optical harvesting source rather than a programmable supply, it enables realistic charge-operate-shutdown characterization. Waveform-level measurements confirm repeatable operation over more than 300 consecutive intermittent cold-start cycles, with no bit errors observed in an ID-transmission workload, indicating deterministic restart under harvested energy. Measured intermittent behavior includes 50-697 s charge times as a function of light level, a regulator rise time of approximately 20 mu s, and an average operating window of 1.17 s across 37 cycles.
IoT ultraviolet (UV) sensors face an intrinsic tradeoff between ultralow power sensing and energy demanding signal amplification. To resolve this, we report a back illuminated n doped GaN photodetector operating at a near equilibrium 0.1 mV bias voltage, achieving an ultralow 6 pW static power. Utilizing trap assisted photogating effect, the device yields a high 6.42 A/W responsivity and robust nanoampere scale currents. Furthermore, structural photonic engineering enables 365 nm narrowband spectral selectivity with a 21.75 nm full width at half maximum (FWHM). This unamplified configuration directly interfaces with low power analog to digital converters (ADCs), dramatically reducing system level energy overhead for fully sustainable IoT UV monitoring.
For program memory in SoC designs, a critical challenge lies in minimizing retention leakage power and simultaneously optimizing both read operation and write robustness. In contrast, write speed and write power can be traded off. Based on these characteristics, this brief presents a fast read and robust write SRAM for program memory with ultra-low retention leakage. This SRAM employs a novel single-ended 10T bitcell featuring fast read, robust write, and ultra-low retention leakage, complemented by a control-signal maintenance circuit to ensure stability during post-retention power-up. To further verify the proposed design, the 10T SRAM was fabricated in a 22 nm FDSOI process. Measurement results demonstrate that the SRAM can operate at a supply voltage as low as 0.33 V, with a corresponding read energy of 17.14 fl/access-bit and a read frequency of 1.4 MHz at this voltage. Meanwhile, this SRAM retains data down to 0.24 V, with a retention power consumption of 0.029 pW/bit under this condition.
To address voltage overshoot, uncontrolled resonant current, and ZVS failure during startup of high-ratio DC LLC converters caused by parasitic capacitance and effective Q-factor surge, this paper proposes a three-stage soft-start strategy: pre-charge for gentle voltage buildup, open-loop ramping with precise duty cycle calculation to ensure ZVS, and closed-loop steady-state output locking. An equivalent model incorporating transformer parasitic capacitance is established to analyze the mechanism of virtual voltage overshoot, with key parameter design formulas derived. A prototype with a 12 V input and a 180 V output validates the strategy's effectiveness in suppressing startup impacts, achieving full-process ZVS and smooth voltage buildup. This offers an engineering solution for the reliable startup of high-gain LLC converters.
This paper presents a non-isolated high-gain DC-DC converter utilizing a parallel-charged cumulative-discharge boost configuration with a 1:1 coupled inductor for photovoltaic (PV) panel integration with a 48 V DC-bus. The proposed operating principle enables parallel inductor energization and series energy transfer enables a high voltage gain at a reduced duty ratio. For a 48 V output, the converter operates at 29.2% duty ratio while limiting switch voltage stress to 36 V. A quasi-distributed air-gap magnetic design is adopted to mitigate fringing-related proximity losses. A 200 W, 50 Hz prototype achieves 95.8% peak efficiency and stable MPPT under varying irradiance and partial shading conditions.
This paper presents a 2 & times; 32 Gb/s 128-Gb/s/mm single-ended distributed transimpedance amplifier fabricated in a 28-nm CMOS processing technology. To address the area-bandwidth trade-off inherent in conventional distributed amplifiers, a distributed biasing scheme is proposed to eliminate large passive terminations and their associated layout overhead. In addition, a dual m-derived inductor-peaking technique is introduced to extend the bandwidth without channel width penalty. The prototype achieves a per-channel data rate of 32-Gb/s, a 3-dB bandwidth of 24 GHz, a transimpedance gain of 42.9 dB Omega, and an edge bandwidth density of 128 Gb/s/mm.
