This paper promotes the adoption of an automatically-determined nonuniform configuration of base ballasting resistors (R B s) to extend the safe operating area (SOA) of arrays made of paralleled heterojunction bipolar transistors (HBTs). This strategy mitigates electrothermal (ET) effects compared to the standard approach based on a uniform base ballasting distribution, thus delaying the occurrence of the maximum temperature withstandable by the individual HBTs. The optimum set of R B s is calculated through an iterative in-house routine, which makes use of a freeware named TADS interface to connect MATLAB and Keysight ADS. The core of the routine is represented by circuit-based ET simulations in ADS. As a case study, a 14-HBT array in GaAs technology was considered, the optimum R B s set of which was efficiently computed in less than 2 minutes. It is shown that the SOA boundary is significantly pushed rightward with respect to the uniform configuration, without price to pay in terms of bandwidth reduction.
This paper introduces an industry-grade, multi- purpose closed loop flow boiling cooler test stand for rapid experimental characterization and parameter variation. A flow boiling chamber with interchangeable plug-in heater module was designed that allows for the investigation of different finned cooler structures and surface topologies and chemistry respectively to enhance small bubble formation and release. In this experimental investigation a finned and a pin finned cooler structure using mm-size dimensions were used. It could be shown that the pin finned and finned cooler structure show for low flow rates at low pressure drop the same performance. Furthermore, it could be observed that the heat transfer coefficient could be increased for both cooler structure in the two-phase regime as opposed to single-phase convective liquid cooling.
Modifying the geometry of additively manufactured lattice structures holds the potential to improve the thermofluidic characteristics of heat sinks according literature. This study focuses on the investigation of six distinct lattice structure configurations based on the BCCz unit cell. The analysis included two types of cross-sections, namely circular and elliptical, as well as two non-uniform cross-sectional variations along the strut. All six configurations were additively manufactured, with the feasibility of producing elliptical and evolutive cross-sections confirmed through preliminary studies on the 3D printing technique. The effects of varying strut cross-section on heat transfer rates were examined both numerically and experimentally. CFD simulations and experimental measurements agree on the potential enhancement of heat transfer rate.
Reliability of vertical-cavity surface-emitting laser (VCSEL) diodes is essential for e.g. LiDARs, which are used to enable autonomous driving. One crucial parameter for VCSELs is the junction temperature. Higher temperatures reduce the efficiency, shift the wavelength, and reduce the lifetime. The temperature itself depends, among others, on the thermal resistance of the thermal path responsible for heat dissipation. Typically, the thermal resistance of VCSELs is measured using the temperature depended shift of the peak wavelength. However, the sensitivity is very low, which reduces the accuracy, and the measurement duration is long, which inhibits time-resolved inspection. Instead, this paper introduces and verifies the thermal characterization of VCSELs by using the temperature dependence of the forward voltage of the VCSEL. This approach is used similar for LEDs. The method permits the omission of cost-intense spectrometers with high wavelength resolution, increases the accuracy and enables time resolved evaluation. Latter is required for transient thermal analysis (TTA) to measure e.g., the thermal impedance.
Fault clearance time in the power system with renewables generally varies from 0.5-10 cycles (10-667 ms for 50 Hz). Power electronic converters should be able to provide an increased current without exceeding the thermal limits during faults. Accordingly, the heat generated in the semiconductor chip during over-current (OCs) should be removed from the chip as soon as it is generated. In this paper, microchannel (MC) cooling has been investigated through COMSOL simulations for OCs with SiC MOSFETs. The upper limit of the chip temperature has been assumed to be 250 °C as SiC devices do not fail in this temperature range. The duration of OCs is from a few tens of milliseconds to a few seconds. It is concluded that MC cooling has the potential to increase the duration of OC without reaching the assumed upper limit of the temperature.
This paper investigates the thermal performances of four different packages from two different suppliers, both topside and bottom side cooled using 3D CFD simulation. The results show the pros and cons of both solutions.
As the application of micro-electromechanical systems (MEMS) in today’s sensors and actuators have become common, there are still many open questions in terms of analytical analysis, which is related to their operation in multiple physical domains. Beside the numerical analysis it is essential to have a precise view of their behaviour which is required to derive system level models in the later phases of the design process to perform design of experiment (DoE) analysis as well. In this paper the out of plane displacement of bimaterial microbeams is investigated which are the parts of a larger MEMS, designed to use for Kelvin probe measurements. The analytical formula for maximal displacement is derived from the well-known expression using the different coefficients of thermal expansions (CTEs) when a beam composed of two materials is heated. The derived formula is compared to numerical simulation, where an empirical scaling factor is introduced to compensate the inaccuracies. The material and geometry dependence of this scale factor were also investigated and presented in this article.
Forced immersion cooling is an obvious next step from currently available passive immersion datacenter cooling. However, forced convection applications with parallel branches are known to be susceptible to interaction effects where a change in one flow branch causes changed behavior in the other branches. In forced immersion datacenter cooling this can mean that removing a server from a tank will interrupt cooling for the remaining servers, while such removal is foreseeable for reasons of repair and maintenance. CFD simulations on a case study confirm the risk. In the simulated case, removal of one server enclosure leads to 90% less flow and 30% less cooling performance in the remaining ones. A fully passive countermeasure is designed, consisting of a locally perforated plate that acts as an additional large flow resistance. With this in place the loss of cooling performance is limited to 0.5% for removal of one server, and to 5% over all possible empty slot configurations, at the cost of a larger pump and a small increase in pumping power. The case demonstrates that robust design against the effect of flow bypass in a forced convection immersion tank is both necessary and feasible. Tank level CFD simulations are key to find the correct layout and porosity of the resistance plate.
Knowing power losses and the junction temperature for the design of a power converter is crucial and helps sizing its power stage correctly. There are several commercial simulators available, but most of them are targeted for power modules and not for discrete devices. We developed a simulator for power loss evaluation aiming at being able to target different power devices (either discrete or power module) and substrates (PCB or ceramic based). In order to provide accurate simulations, we estimate power losses using a mix of analytical formulae populated with empirical data. The junction temperature is calculated using the analytical solution of a multi-stage Foster network, based on data coming from substrate characterization. The resulting implementation provides fast execution time and a good degree of accuracy.
In this paper, a simple electrothermal compact model for the static behavior of SiC MPS diodes is developed in the form of a SPICE-compatible subcircuit. The model is suited to describe the undesired snapback mechanism likely to occur in unoptimized high-voltage MPS structures with narrow width of the PiN portion and/or very thick drift layer. The electrothermal simulation is enabled by resorting to the thermal-electrical analogy. Sentaurus TCAD simulations of a 10 kV MPS diode are used as a reference for the calibration of the model parameters and accuracy verification.
This paper presents a new open-source simulator that aims to provide a tool to study a wide range of current and future problems requiring high-resolution distributed simula tion in engineering practice, especially in microelectronics. The problem to be studied is defined as a circuit model, which can be specified by a SPICE-like description. The simulator solves this circuit using the highly efficient Successive Network Reduction Method, optimized specifically for solving circuit models of fields discretized by the Finite Differences or Finite Volumes methods. The circuits can be extended with programmable special components: controllers, to easily implement special tasks such as hysteresis or ray tracing modelling.
In this work, a Thermal Test Vehicle (TTV) is developed to demonstrate the thermal characterization utilities for large die area packages. The TTV consists of a silicon Thermal Test Chip (TTC) on organic interposer assembled with lid and thermally conductive adhesive as thermal interface material. The setup mimics the system-level application and the use of the transient thermal characterization method studying the local thermal impedance as thermal heat path signature Rth(x,y) for achieving spatial resolution with high granularity in the location of heat dissipation.To obtain a more comprehensive understanding of the thermal behavior, the structure function is determined and helps to characterize the spatially resolved heat transport through the layers of the large die area package architecture. Furthermore, the thermal influence of possible defects such as warpage, delamination or voids within the structure is investigated and how the power density distribution on chip level affects the thermal behavior.
This study investigated the thermal performance of a packaging solution designed to manage the electrical isolation and cooling of high voltage (> 3300 V) SiC power semiconductor devices. The proposed packaging merges the ceramic substrate and the heat exchanger into a single component, streamlining the overall design. Specifically, a novel heat exchanger is developed for a multi-chip module (20kV), utilizing a combination of jet impingement and channel-flow cooling techniques. Computational fluid dynamics (CFD) simulations and experimental validation are conducted on a multi-chip module to assess the thermal resistance of this new cooling solution. The results demonstrate a low thermal resistivity of 0.118cm 2 K/W, indicating the potential for improved cooling performance in high voltage and power density semiconductor applications.
This paper analyzes four junction temperature estimation’s strategies using CFD simulation, highlighting the advantages and limitations for each of them. Then an implementation on real hardware of one of the previously analyzed strategies is presented.
In this work the heat transfer of a PV solar module is investigated with CFD simulations. Conjugate heat transfer simulations are created, in which the air flow with the convective heat transfer around the solar panel and the heat transfer inside the PV module are both simulated. The radiative heat transfer is also modelled using the discrete ordinates method. First, the PV panel is simulated without wind flow, where the module induces a buoyant flow of warm air. Then, several cases are investigated with wind flow, considering different wind speeds and wind directions around the panel.
We developed a simple and inexpensive feedback regulated high cycle fatigue (HCF) testing device intended to simplify the reliability assessment of macroscopic thin metal film specimens taken right out of the fabrication line of electronic devices and proved its effectiveness in inflicting fatigue damage in thin copper films under HCF regime within a reasonable amount of time. A cm-sized steel cantilever carrying a macroscopic thin film specimen is brought to its resonance vibration by cyclic excitation using an electromagnetic (EM) coil. The reflection of a laser beam, off the surface of the cantilever tip and some optical elements and a photodiode is used to calculate vibration amplitude using optical principles and a feedback control loop regulates that vibration amplitude during fatigue experiment. As a testing sample, an organic board with electroplated copper thin film is fatigue loaded using the developed device and intermittently studied under optical microscope (OM). The OM images show the fatigue damage evolution manifested as dark patches on the film surface and also development of fatigue macro cracks and their growth. The scanning electron microscope (SEM) micrographs of the sample at crack points confirm that only the copper film suffered fatigue cracking and the organic board underneath remained intact.
We present a novel design of experiments approach for LEDs based on Gaussian processes. The method aims to decrease the measurement effort associated with characterizing LEDs based on their spectral power distribution (SPD) and derived quantities of interest (QOIs), such as the luminous flux or color coordinates. It is both easy to implement and based on open source software. We showcase the approach on an example taken from automotive applications. For the considered example, we are able to decrease the total number of measurements by over 75%, while the model is able to predict the SPD and derived QOIs with relative errors of less than 5%.
A reduced-order model (ROM) has been extended and applied to counter-rotating (CR) dual impeller fans commonly employed in cooling electronics enclosures of data centre systems. The model incorporates the actual rotor and stator geometry, and its accuracy was assessed against experimental fan performance ( P-Q) curve data, as well as compared with computational fluid dynamics (CFD) results. Additionally, the influences of stator and radial flow were explored through CFD simulations. The limitations of the ROM were further discussed. The ROM’s predictions exhibit favourable agreement with experimental and numerical findings, with normalised rootmean-square errors of 4.6% in the normal working region and 13.2% in the stall region. Notably, the ROM offers significant computational savings compared to CFD simulations, rendering it a valuable cost-effective tool for preliminary design, analysis, and optimisation of CR fans.
This study analyses the effect that leading edge geometry has on the thermal performance of plate fin heat sinks in forced convection. The range of Reynolds numbers studied covers the so-called transitional flow regime, where laminar- turbulent transitional flow can exist even above critical Reynolds numbers. Plate fins with sharp (rectangular) and rounded leading edges are considered. 2D numerical analysis on forced convection over the fins is carried out in ANSYS Fluent using the Transition SST turbulence model to capture transitional effects. At lower Reynolds numbers, a fully laminar boundary layer exists along both the sharp and rounded fins, with the sharp fin exhibiting slightly lower heat transfer rates and higher flow resistance due to large flow separation at its leading edge. Above a critical Reynolds number, separation-induced transition occurs at the leading edge of the sharp fin, creating a turbulent boundary layer along the fin. This increases the average Nusselt number of the sharp fin by 58 - 186% relative to the rounded fin. Using a Quality Factor metric, defined as the ratio of heat transfer rate to pumping power across the fin, the sharp fin was found to have a 24.6 - 70.1% higher thermal efficiency than the rounded fin above the critical Reynolds number. These results suggest that in the transitional flow regime, a sharp leading edge increases the thermal performance of plate fin heat sinks by promoting turbulent forced convection along the fins.
Thermal management of electronics continues to be a dominant factor that needs attention already early in the design phase. Within complex systems, typically a battle for space is imminent due to the multidisciplinary nature. In this respect, the use of low-form-factor phase-transitional devices is standard industry practice nowadays. In particular, heat pipes have demonstrated high heat transfer rates, due to the utilization of a working fluid’s latent heat in combination with reliable, small and lightweight designs. Heat pipes are employed in electronics cooling in which they are often bent and operated under different perating conditions. This study aims to investigate how heat pipes function when bent at various angles and inclinations. The impact of various bending angles (no bend, 30° bend, 2x30° bend, 45° bend, 2x45° bend and 90° bend) and inclination angles (horizontal, ±45° and ±90°) is examined. Bending losses and an associated theoretical model are validated for sintered-wick heat pipes. Heat pipe bending has minimal effect on the thermal performance as long as the bending angle does not exceed 45°. It is however important to consider gravity when operating bent heat pipes outside the horizontal plane.
