Recently, major semiconductor manufacturers have developed spin-transfer torque magnetic random-access memory (STT-MRAM) embedded in logic node due to its superior properties. In order to leverage high performance in advanced logic node, it continues to scale down logic node from 28nm to 14nm and 8nm. As device dimensions shrink, variability in magnetic and electrical properties increases, impacting data retention, endurance, and read/write performance. In this paper, we review the overall reliability trends, highlighting specific reliability factors that demonstrate significant scaling dependence.
Gate dielectric time-dependent dielectric breakdown (TDDB) is a critical reliability concern in FinFET devices. However, the microscopic failure mechanism of on-state TDDB (|V-gs|>0, |V-ds|>0) is different from V-gs-only TDDB (|V-gs|>0, |V-ds|=0) due to the impact of channel current. In this study, aberration-corrected scanning transmission electron microscopy (STEM) and advanced strain analysis are employed to observe the physical evolution during the breakdown process of FinFETs from an atomic perspective. It is discovered that breakdowninduced silicon epitaxial defects are generated at the corners of the fin for Vgs-only TDDB, while shifted to the middle of the fin for on-state TDDB. The formation of these defects on the Si <110> orientation is accompanied by tensile strain. This work provides new insights into different types of TDDB phenomena in FinFETs at the atomic scale.
Electrostatic discharge (ESD) protection design for radio-frequency integrated circuits (RFICs) and high-speed I/O circuits is a challenge due to the parasitic capacitance generated from ESD devices, which significantly degrades circuit performance under high-frequency/high-speed operation. Striking a balance between effective ESD protection and maintaining high-frequency/high-speed circuit performance is strongly requested by IC industry. In this work, an improved layout is proposed to significantly reduce the parasitic capacitance of the diode-trigger silicon-controlled rectifier (DTSCR) device while maintaining high ESD robustness. The DTSCR with improved layout has been verified in a 28-nm fully-silicide CMOS process with the experimental result of high ESD robustness per unit capacitance, which is suitable for on-chip ESD protection design with low-C requirement.
AC TDDB (Time-Dependent-Dielectric-Breakdown) lifetime exhibits inconsistency at low frequencies (<10kHz), while it is reported to be longer at higher frequencies. In this study, AC TDDB mechanism is systematically investigated over a frequency range of 2Hz to 500kHz. Notably, n-type transistors with bi-layer gate stack demonstrate degradation of AC TDDB lifetime below that of DC TDDB in both FinFET and Planar devices. This degradation worsens as the gate oxide thickness decreases, a phenomenon explained by Maxwell-Wagner instability. To mitigate this degradation at low frequencies (LF), applying a small positive voltage during the off-state of the AC pulse (Vr) can improve reliability, particularly in circuits operating at low frequencies.
