In this paper, we discuss a new development of 40nm SONOS eSTM™ (embedded Select in Trench Memory). We present an experimental study based on hot carrier injection mechanism for both programming/erase operations, performed on this new eNVM architecture. The optimization of drain and select gate biases, in order to define the programming and erasing threshold voltages, is also detailed. All the characterizations have been carried out for two different SONOS eSTM™ architectures giving an opportunity to propose different solutions. One of this using a continuous silicon nitride layer for two neighbour cells, taking advantage on the discrete charge trapping nature. As well, we performed endurance tests up to one million cycles for both architectures to evaluate the memory endurance.
This work presents a comprehensive analysis of electrothermal effects in emerging 3D vertical junctionless nanowire transistors (VNWFETs) using on-wafer measurements under a wide range of temperature and validated against numerical and compact model simulations. Experimental observations indicate an increase of the drain current with the temperature, conforming to the behavior of junctionless FETs. Multiphysics simulations reveal formation of temperature hot-spots that adversely affect thermal conductivity in smaller geometries. The VNWFET compact model was then modified to account for the underlying electro-thermal effects as well as dynamic self-heating. Model simulations and the experimental results at different measurement temperatures for different transistor geometries show good agreement. The developed SPICE-compatible compact model was then used for studying the impact of electrothermal effects on the performances of basic 3D logic circuits.
We present an analytical model to reproduce the non-monotonic temperature dependence of Time-Dependent Dielectric Breakdown (TDDB) in galvanic isolators based on polymeric dielectrics. The model is based on the concurrent action of two competing mechanisms involved in the TDDB dynamics, namely the worsening of the polymer dielectric strength due to moisture and the outdiffusion of water molecules during the electrical stress phase. By catching the most relevant features of the temperature dependence of TDDB in a simple yet effective way, the model represents a valuable tool to support the design of galvanic isolators based on polymeric dielectrics.
In this work, we investigate the intrinsic cycle-to-cycle variations in a spiking temperature-sensitive neuron, based on the resistive switching of a Vanadium dioxide (VO 2 ) two-terminal device. We study how this phenomenon impacts the spike rate jitter, and affects the spiking sensor precision. To do so, we combine a statistical analysis of the device DC characteristics, with measurements of the spiking neuron in dynamic operation from 41 to 47 °C. Using an analytical dynamic model, we reveal that the VO 2 cycle-to-cycle variations of the insulating resistance and insulator-to-metal threshold voltage dominate the stochastic processes. Our spiking sensor achieves large, linear sensitivity (1.71 kHz/°C) and high resolution (0.024 °C for a 10 ms-long observation), attributed to its small cycle-to-cycle variations.
