This paper presents an OIF CEI-1125G-XSR compliant short-reach SerDes with data rate from 9.8 to 113Gb/s PAM4/NRZ, implemented in 3nm finfet technology. The quarter-rate source-series terminated (SST) transmitter is im-plemented with 2UI-delay based MUX, supply adjusted and impedance calibrated DAC driver to maintain constant TX swing across PVT. The receiver utilizes a unique AC-coupling-based method before and after single-stage CTLE with 4 edge and 12 data samplers. The design has a standard 3 taps FFE and an optional 6 taps FFE, as well as continuous adapted RX CTLE to track temperature drift and achieve BER<le-14 below 8dB and <le-12 for loss up to 10dB on both 2D and advanced 2.5D CoWoS package.
This paper introduces a digital dynamic vision sensor (DVS) with single-photon avalanche diode (SPAD). The sensor operates in a fully digital manner, eliminating circuit noise and non-uniformity. To provide a motion-adaptive optimum frame rate and minimize vibration-event noise (VEN) caused by sensor vibrations, the sensor generates multiple events via quantized delta (QD) signal. Thanks to the QD, the sensor detects the relative speed of moving objects, adjust the frame rate accordingly, and filter out VEN, thereby allowing only essential events from the objects. Furthermore, the sensor incorporates event-driven threshold control (EDTC) logic to ensure the optimal number of events. The EDTC and VEN filter offers data reduction of 72.8% and 64.5%, respectively.
This paper presents a 20-Gb/s/line current-mode transceiver for dense short-reach on-chip interconnect. The transceiver achieves a systematic crosstalk cancellation (XTC) by balancing the crosstalk induced by capacitive and inductive coupling. As a receiver frontend, a current-sensing amplifier is designed with an optimum input resistance value for XTC. Without any additional circuits for XTC and equalization, the transceiver implemented in a 40nm CMOS technology shows an energy efficiency of 246fJ/b and an edge bandwidth density of I3.3Tb/s/mm, even with shield-less $1.5-\mu \mathrm{m}$ pitch and I-mm length channels.
2D transition metal dichalcogenides (TMDs) show promise for transistor scaling, but their on-scale performance had not been proven yet. This work demonstrates contact length (Lc) scaling while holding a low contact resistance (R C ) down to 11 nm. Channel length $(\mathrm{L}_{\text{CH}})$ scaling shows I ON can increase down to at least 12 nm with low Rc. The very scaled $(\mathrm{L}_{\text{CH }}=19$ nm and $\mathrm{L}_{\mathrm{C}}=12$ nm) Mos2 transistor with Sb-based metal contact has current density of ~1130 μA/μm at $\mathrm{V}_{\text{DS}}$ = 1 V, and a low $\mathrm{R}_{C}$ of ~ 190 Ω.μm. These scaled transistors, processed within a back-end-of-line (BEOL) thermal budget, do not exhibit subthreshold swing (S.S.) degradation or observable drain-induced barrier lowering (DIBL) down to $\mathrm{L}_{\text{CH}}=12\text{nm}$ .
