This article presents a compact 64-98GHz power-combining frequency doubler with magnetic enhanced harmonic reflectors. The 2(nd) harmonic outputs of two identical push-push frequency doublers are combined to improve the maximum output power. Two ways share an L-C harmonic reflector, and each way employs a C-L harmonic reflector. Two C-L harmonic reflectors are magnetically coupled to enhance each other and save area. Fabricated in a 65-nm bulk CMOS technology, the doubler achieves a 3dB bandwidth of 64-98GHz, a peak saturation output power of 11.4dBm, a maximum drain efficiency of 21.1%, a maximum conversion gain of 3.3dB, with a core area of only 0.053mm2.
This brief presents a 112 GS/s 7-bit 64-channel time-interleaved (TI) hybrid ADC fabricated in 28-nm CMOS. A T-coil input network combined with two-rank hierarchical samplers extends the input bandwidth and concurrently relaxes the clocking requirements, while the reduced rank-1 sampling capacitance facilitates high-speed operation. Low-jitter, low-skew, and power-efficient sampling clocks are generated by an injection-locked ring oscillator (IL-ROSC) together with background time-skew calibration. The sub-ADCs adopt a hybrid architecture to achieve a 1.75 GS/s sampling rate, effectively reducing interleaving complexity while maintaining linearity. The prototype ADC operates from 1 V/1.7 V supplies, achieving 27.1 dB SNDR and 43.1 dB SFDR at 44.1 GHz, with a core area of 0.343 mm(2) and a power consumption of 968.7 mW.
This brief presents a 3-D integrated 6-18 GHz reconfigurable filtering low-noise amplifier (LNA) using a GaAs pHEMT MMIC and a vertically stacked GaAs hyper-abrupt varactor die. The vertically integrated varactors are employed as the voltage-controlled tuning elements in the reconfigurable filtering networks, enabling wide-range passband tuning beyond that achievable with MMIC-compatible varactors. Two switch-selected reconfigurable filtering paths cover the 6-12 GHz and 12-18 GHz sub-bands, enabling continuous narrowband passband tuning within the two sub-bands across the overall operating range. The transmission-zero tuning behavior and the EM-extracted vertical-transition response are considered in the circuit/EM co-design. The fabricated stacked chip occupies 3.8 mm & times; 2.5 mm. Measured results show 28.5-32.5 dB gain, 0.9-1.25 dB NF, OP1dB above 15.2 dBm, and a typical out-of-band rejection of 40 dBc.
This brief presents the fabrication and experimental validation of an interlaced 6T-11T CMOS in-memory computing circuit designed for low-silicon-area pipelined binary neural networks. The circuit implements a weight-stationary architecture in which input activation values are sequentially stored in 6T SRAM columns, while 11T cells retain the convolution weights and perform binary XNOR-based multiply-and-accumulate operations, naturally aligning with the column-parallel readout topology of CMOS image sensors. The circuit has been fabricated in a 180 nm standard CMOS process and experimentally characterized. Measured results on a binary convolutional layer demonstrate operation at 1 MHz with a simulation-assisted energy efficiency of 18.53 TOPS/W. The interlaced organization embeds the line-buffer functionality required for streamed convolution within the IMC array itself, so that image rows are processed as they are read out from the sensor.
This brief proposes a novel asymmetric impedance compression network (AICN) inverter system for wide resistive-inductive load impedance operation. To decouple the inverter behavior and load impedance variation, the branch load impedances are required to be purely resistive for load-independent (LI) design. Therefore, the high frequency (HF) single-switch resonant inverters under LI design can function as ideal ac sources and realize soft switching. Further, the ac output can be modulated by adjusting input voltage amplitudes and phase differences of two branches. Based on single-branch regulation, experimental validation was conducted with a 13.56 MHz prototype capable of delivering constant 100V ac output voltage, with measured peak efficiency reaching 90.94%.
