As an imperative part of supporting 5G-A/6G base station, baseband processor encounters more challenging key performance indicator requirements. The existing hardware designs for baseband processor have difficulty in achieving high flexibility, low latency and high throughput with high hardware and energy efficiency. We propose a baseband processor based on ASIP (Application Specific Instruction-set Processor) design philosophy and dynamic coarse-grained reconfigurable array (CGRA), which can enable flexible and scalable baseband processing operations in 5G-A/6G base station, and delivers three important merits: high throughput (56 Gb/s), low latency (0.9 ms) and high flexibility. Instruction fusion is a critical approach in ASIP to enhance computational performance and energy efficiency, we design dependency tracker and light-weight hardware resource table to eliminate data and structural hazards that arise from instruction fusion in ASIP, which utilizes low silicon costs to achieve performance improvements. Moreover, we propose parallel and conflict-free data addressing method with low storage overhead to minimize memory access latency. Fabricated in a 16 nm CMOS technology, our processor achieves high flexibility and high performance in supporting various baseband processing tasks and various MIMO scales for 5G-A/ 6G base station. Our processor achieves 889-10000Gb/s/W energy efficiency and 35-130 Gb/s/mm(2) area efficiency for detection and decoding tasks, which are 1.2-85 & times; and 2-42.6 & times; those of state-of-the-art hardware designs respectively. To our knowledge, this is the first high flexible and high-performance baseband processor for 5G-A/ 6G base station.
A dual-source single-inductor dual-output harvester is proposed for solar and piezoelectric energy harvesting. Based on the efficiency characteristics of inductive switching converters and the electrical characteristics of ambient energy sources, the converter adopts an efficiency-oriented reconfiguration strategy to match varying ambient energy conditions. It operates under a load-priority principle, supplying the load directly before storing surplus energy. Moreover, a specialized driver for the output-side PMOS switches is designed to accommodate large voltage difference between the dual outputs. The proposed harvester is fabricated with a 0.18 mu m CMOS process. The experimental results demonstrate that it achieves a peak efficiency of 84.6% while harvesting energy.
This paper presents a dual-time-window-sampling CMOS temperature sensor based on subthreshold current for always-on AIoT temperature monitoring. By using time-division multiplexing, the same sensing core is reused across two consecutive time windows to sequentially generate two temperature-dependent currents, and temperature readout is achieved through frequency-ratio-to-digital conversion, thereby effectively reducing mismatch sensitivity. Fabricated in a 55-nm CMOS process without requiring explicit resistor or capacitor devices, the sensor occupies a compact area of only 0.0047 mm(2). At 25 degrees C, the temperature sensor consumes a weighted average power of only 5.3 nW with a 0.5 V low-voltage-domain supply and a 1.2 V gate-voltage-generator control supply. Measurements show an average inter-chip relative standard deviation of 7.55% for the digital temperature code over the temperature range from-40 degrees C to 100 degrees C. After 2-point calibration, the measured maximum temperature inaccuracy is +1.58 degrees C/-1.73 degrees C over the same temperature range. The proposed sensor simultaneously achieves ultra-low power, compact silicon area and a wide temperature range.
EVA is an accelerator designed for evolvable edge computing applications. It integrates programmable processing array tiles (A-Tiles) for performance and utilization, and RISC-V CPU tiles (C-Tiles) for control and full-chip reconfiguration in about 110cycles. EVA features a versatile interconnect fabric, a distributed memory system, and flexible mapping. A16mm(2) EVA test chip achieves a peak throughput of 1.54 TFLOPS (FP16) with an energy efficiency of 196GFLOPS/W at 0.9V. At 0.49V, EVA delivers 111 GFLOPS (FP16) while achieving a peak energy efficiency of 708GFLOPS/W, demonstrating high compute density and efficiency for diverse workloads.
This paper presents a 4-7GHz cryogenic readout integrated circuit (ROIC) implemented in a 65-nm CMOS process for superconducting multi-qubit readout. The proposed ROIC front-end employs a transformer (TF)-based dual-path noise-canceling low-noise amplifier and a TF-based current-bleeding active mixer to enhance gain while suppressing thermal and flicker noise. To realize a wide dynamic range and a large intermediate frequency (IF) bandwidth, a dB-linear broadband (435MHz) variable-gain amplifier with an active-RC feedback topology is employed for multi-qubit sensing. The fabricated ROIC operates at a cryogenic temperature (13K), achieving a maximum gain of 70.4dB and a minimum noise figure of 0.41dB (29K noise temperature) over 435MHz IF bandwidth. The input 1-dB compression point and the input third-order intercept point reach-59.8dBm and-50.4dBm at the maximum gain setting, and-29.8dBm and-20.7dBm at the minimum gain setting, respectively. The ROIC achieves a spurious-free dynamic range of 30.8dB and 50.6dB at maximum and minimum gain settings, respectively, demonstrating competitive performance among reported cryogenic ROICs. The prototype consumes 16.3mW from a 1.2-V supply at 13K with an active area of 1.45 mm(2).
