Ferroelectric Tunnel Junction (FTJ) is an emerging non-volatile memory technology with increasing applications in storage and computing. The low programming energy of these devices make them an excellent candidate for low-power and power constrained applications. The multi-bit capability of these devices is exploited for Matrix Vector Multiplication in memory. To program the FTJ devices to multiple states, on-chip READ and WRITE circuits are necessary. In this work, we first present the programming circuit for multi-bit FTJ. Our circuit is able to generate pulse of two different amplitude from the input pulse and apply them across the FTJ. The READ circuit is able to convert the polarization state of the FTJ (which is represented in pA currents) to a CMOS-compatible voltage. The presented circuit occupies low area in addition to being energy-efficient. The presented circuits can be adapted for other NVMs and has a strong potential to find immense application in In-Memory Computing.
This brief presents a 10 Gb/s low-power single-ended linear equalizer for DRAM interfaces in 12nm FinFET technology. The proposed architecture consists of a continuous-time linear equalizer (CTLE) to compensate for the channel loss followed by a variable gain amplifier (VGA) to enhance the DC gain and sampling margin. The gain of the VGA is controlled by changing the source current, which can improve the power efficiency of the receiver based on the channel loss. Furthermore, another two common multi-stage equalizer approaches including two-stage CTLE and single-ended gain amplifier followed by a CTLE were designed and simulated in the same technology to compare with the proposed architecture. The simulation results show that the proposed linear equalizer exhibits the best overall performance in terms of power dissipation, area and eye height. The proposed equalizer consumes 0.94 mW at the Nyquist frequency of 5 GHz and 0.8 V supply voltage. It also compensates for a channel loss of 15 dB with a figure-of-merit (FoM) of 6.26 fJ/bit/dB, surpassing other previous works.
The Sets Of Real Numbers (SORN) format is a derivation of the universal numbers (unums) and represents an interval-based, low precision number format. It relies on lookup table (LUT) arithmetic, which can be implemented as ROM-like logic circuits. Previous works have evaluated the format for different use cases and applications, mostly under the assumption that the format can only be applied efficiently for bitwidths below 20 bit, because of the increasing complexity of the LUTs. This work evaluates on this assumption by implementing SORN addition and multiplication for different SORN datatypes and bitwidths between 5 and 31 bit, and comparing the resulting hardware circuits to standard integer implementations. The findings in this work show that SORN arithmetic actually scales quite well with bitwidth and mostly outperforms integer arithmetic in terms of hardware measures. Solely the area requirements of the SORN addition modules are higher than for integer designs of same bitwidth, whereas for multiplication a significant area reduction of up to 80% can be achieved. Further, the SORN modules are at least twice as fast as integer, and reduce the power consumption by up to 50% and 97% for addition and multiplication, respectively.
Application-specific instruction-set processors (ASIPs) can yield significantly better performance and energy efficiency results compared to general-purpose processors, while maintaining programmability. Instruction set customization raises the issue of how to integrate co-processors implementing custom instructions with the datapath, as using microarchitecture-specific interfaces lead to difficulties reusing them for other processors. Equally important is applying automatically retargeting compilation for the custom instructions to ensure easy utilization. To this end, we introduce a method for constructing an automatically retargeting compiler toolchain and a flow for generating Core-V eXtension interface compatible co-processors that can adapt to the same architecture description. We demonstrate the toolset by designing an ASIP based on the CVA6 processor for three BEEBS benchmark suite applications, which reduces the execution time 26% on average with an area overhead of 1% without affecting the clock frequency of the synthesized hardware implementation.
This paper describes a novel on-chip digital aging sensor circuit capable of detecting MOS transistors wearout due to negative-bias temperature instability (NBTI). The proposed aging sensor circuit enables us to identify the $V_{t h}$ shift of a pMOS transistor only from the sensing outputs without building simulation models or complex calibration procedures. To achieve this, the proposed circuit monitors the leakage-current based charge accumulation speed that is affected by a stressed pMOS power switch. We designed and implemented a test chip in a 65nm FDSOI CMOS technology. By operating the fabricated test chip at an ultra-low voltage (i.e. 0.3 V), we observed a clear linear relationship between the logarithm of the charge accumulation time and the reciprocal of the temperature, which is indicated in derived analytical expressions. From the slope value of the linear relationship, the rate of increase in ${V}_{t h}$ due to stress was successfully obtained. We also demonstrate that the proposed aging sensor circuit can detect aging at actual use at a nominal voltage.
Distributed massive MIMO systems are expected to be part of the upcoming generation of wireless systems where joint communication and positioning opens the possibility of exploring new applications. In this work we investigate one of the various ways of deploying these kinds of systems, through the concept of Large Intelligent Surfaces (LISs). Although the concept of LISs is not completely novel, practical realization of such systems is still lacking. We propose a highly accurate, low latency indoor distributed positioning multi-FPGA solution which leverages the particularities of a machine learning algorithm to obtain resource efficient hardware accelerators. We make use of the common infrastructure of the physical layer within a wireless network to explore the reusability and scalability of our design.
This paper introduces an MMIC radiometer receiver designed for integration into a 240 GHz radiometer receiver system using a 130-nm SiGe BiCMOS technology. The detector features an on-chip dipole antenna, an SPDT switch, a Low Noise Amplifier (LNA), a mixer, an IF amplifier, and a power detector. The resonator switch exhibits a measured minimum insertion loss of 4.2 dB, maximum isolation of 29 dB, and minimum input and output reflection coefficients of 16 dB and 20 dB, respectively. The LNA utilizes a 5-stage cascode design, achieving a simulated gain of 28 dB at 240 GHz. The mixer, designed as a single-balanced second harmonic mixer, provides a simulated conversion gain of 0 dB. The IF amplifier, a 3-stage differential cascode amplifier, can provide a simulated gain of 45 dB at its IF frequency. The power detector is designed using the Meyer topology for a high dynamic range contributing to the chip's ability to enhance radiometer resolution. Additionally, this paper also presents a free-space measurement conducted to verify the radiometer receiver's functionality. In the measurement, with a LO frequency set at 112 GHz, the detector provides an output voltage of 650 mV in response to an IF current of 43 mA, demonstrating its effective performance.
The increasing demand for real-time low-power hardware processing systems, endowed with the capacity to perform compute-intensive applications, accentuated the inadequacy of the conventional architecture of multicore general-purpose processors. In an effort to meet this demand, edge computing hardware accelerators have come to the forefront, notably with regard to deep learning and robotic systems. This paper explores preeminent hardware accelerators and examines the performance, accuracy, and power consumption of a GPU and an FPGA-based platform, specifically designed for edge computing applications. The experiments were conducted using three deep neural network models, namely AlexNet, GoogLeNet, and ResNet-18, trained to perform binary image classification in a known environment. Our results demonstrate that the FPGA-based platform, particularly a Kria KV260 Vision AI starter kit, exhibited an inference speed of up to nine and a half times faster than that of the GPU-based Jetson Nano developer kit. Additionally, the empirical findings of this work reported as much as a quintuple efficiency over the Jetson Nano in terms of inference speed per watt with a mere 5.4% drop in accuracy caused by the quantization process required by the FPGA. However, the Jetson Nano showed a 1.6 times faster inference rate with the AlexNet model over the KV260 and its deployment process proved to be less challenging.
Molecular property prediction is a critical task in computer-aided drug discovery workflows. In this context, representing molecules as graph structures has become a common approach, leading to the development of graph-based neural networks (GNNs). A prominent type of GNN are the graph convolution network (GCN) that incorporates a number of graph convolution layers followed by fully connected layers in the form of multi layer perceptrons (MLP). Addressing the need for enhanced efficiency, this paper introduces an innovative approach that maps different computation types to specialized accelerators in a heterogeneous edge platform. The proposed system integrates an FPGA accelerator for the sparse operations present in the GCN layer and an Edge TPU for ordinary dense operations in the fully connected layer. The FPGA accelerator is described using High-Level Synthesis (HLS) and optimized to handle the sparsity found on the graph structure and node features while the Edge TPU deploys a systolic array of MAC units optimized for dense matrix multiplication. This hardware/software co-designed GCN+MLP architecture utilizes Pynq and TensorFlow Lite Runtime functions, executed on a multi-core ARM CPU available in an AMD/Xilinx Zynq ultrascale+ device, in conjunction with the Edge TPU and programmable logic. Our results demonstrate performance improvements, achieving speedups of up to 47x compared to traditional software implementations.
In this study, we conduct a systematic comparison of various countermeasures against power side-channel attacks on RISC-V-based Systems-on-Chip implemented on an FPGA. Focusing on the AES cryptographic algorithm running on a RISC-V Ibex core, we evaluate a range of countermeasures, including software masking, hardware/software noise generation, and dummy instruction insertion. We also examine the impact of unprotected software implementations on the specialized CoCo-Ibex micro-architecture by evaluating the Tiny-AES implementation. Our findings reveal significant trade-offs between security and overhead, offering critical insights for selecting appropriate countermeasures tailored to the specific requirements of resource and energy-constrained systems.
The energy efficiency of IoT devices must be improved to improve their computation performance owing to the advancements in IoT technology. In this study, we present a CMOS clock generator with low frequency, high supply voltage, and low power without using step-down converters, which helps in the development of scaling-friendly IoTs. We achieved low-frequency clock generation with low power consumption without using a scaling-unfriendly step-down converter by stacking supply voltages among an oscillator and cascaded frequency dividers. The prototype chip fabricated using the 65 nm CMOS approach demonstrated a clock generation of 2 Hz with power of 0.22 nW and voltage supply of 1.2 V, which is the lowest power achieved at a foundry-recommended nominal voltage in a sub-10-Hz clock generator. The proposed architecture presents potential advantages in advanced technology nodes considering the technology scaling.
As RISC-V processors become more widely distributed, security issues arise. To this end, security verification techniques for processors should be incorporated into the design process to ensure the processor specifications, security requirements, and its actual implementation are consistent. Among the verification techniques, assertion-based verification has emerged as one of the most promising techniques. Although assertions are widely used for functional verification, there is limited effort in applying assertions for security verification. Thus, in this work, a novel security assertion-based technique is introduced for verifying the invulnerability of the processors against Trojan attacks. The experiments show that the proposed method can automatically generate security assertions in a very short amount of time and detect all the inserted Hardware Trojans in the processor, thereby accurately verifying the security of the processor.
Fast evaluation is important for processor design space exploration in order to increase the probability of encountering the optimal design in the vast space of configurations. Previous work has focused on estimation of dynamic multi-issue processors, which does not consider the effects of a varying instruction-set on the estimation through heuristic compilation. This paper presents a cycle count estimation method for application-specific static multi-issue processors with customizable datapaths via machine learning techniques that can estimate cycle counts for any architecture configuration after the initial profiling of the program. Among the estimated models, the residual neural network model achieves the lowest mean relative error of 4.7% while being orders of magnitude faster than running the recompilation and simulation steps.
In recent years, several approaches have proposed dynamic voltage-frequency scaling (DVFS) controllers for power management in multiprocessor system-on-chips based on reinforcement learning (RL) to cope with changing system dynamics. Those implemented in software cannot respond to short-term changes in processor load, which occur at a sub-millisecond scale. On the other hand, modern processors contain various built-in hardware features, like prefetchers, reacting to short-term variations to improve system performance. Previously, we integrated such an RL-based DVFS algorithm into the hardware and applied it to optimize the performance of best-effort tasks. In this work, we augment it with preemptive shielding and eligibility traces to employ it on deadline-bound quality of service (QoS) tasks. The algorithm takes advantage of short-term variations to minimize power usage while ensuring the application’s QoS. Additionally, our algorithm complies with the power constraints necessary in mixed-critical systems unlike state-of-the-art algorithms. We demonstrate the features of our algorithm in a hardware-in-the-loop simulation by running LLVM’s single-source benchmarks on SparcV8 processors.
Processor systems in control-oriented applications, such as safety-critical real-time systems, rely on low-latency context switching to service multiple tasks in a concurrent yet timely fashion. Conventional microcontroller systems rely on software-based storing and restoring of the active program context, while some microcontrollers have been optimized to accelerate the stacking of the context with custom hardware. However, these solutions do not address the fundamentally sequential nature of context saving. This publication presents a novel approach to parallelizing context saving and restoring by developing a parallel context stack. We integrate the solution into an existing open-source RISC-V processor and microcontroller platform and demonstrate the effective elimination of the context switch latency from the total interrupt latency. The design is synthesized with a commercial application-specific integrated circuit (ASIC) flow, using an open 45 nm technology library, and achieves a maximal frequency estimate of 500 MHz. The presented solution achieves a best-in-class total interrupt latency of 4 clock cycles, without increasing the critical path delay of the processor. We present a comparison of existing hardware mechanisms for context switching and an argument for improved safety and predictability with isolated context saving.
The ZuSE-KI-Mobil (ZuKIMo) project, a nationally funded initiative, focuses on creating an advanced ecosystem optimized for AI-driven applications in automotive, drone, and industrial domains. At the heart of this effort is a state-of-the-art System-on-Chip (SoC), successfully taped out using 22 nm FDX technology, integrating a novel AI accelerator tailored to specific use case requirements, along with proof-of-concept demonstrators that validate the platform's real-world application potential. Key aspects include the customized compiler flow, the hardware generation process of the novel AI accelerator, and the acceleration of different applications using the ZuKIMo platform. Examples of these applications are 3D object detection and disengagement prediction in autonomous driving. The paper provides an overview of the ZuKIMo ecosystem, highlighting its contributions to AI performance, energy efficiency, and safety in heterogeneous AI hardware platforms.
The settling behavior of OTAs in CIFB and FIR-feedback Switched-Capacitor Delta Sigma modulators is analyzed, focusing on the trade-offs between power consumption and resolution. A settling error model highlights the impact of slewing non-linearities, with simulations showing that FIR filters reduce Slew Rate (SR) requirements and lower power consumption, making Gain-Bandwidth (GBW) the primary limiting factor. However, FIR benefits diminish at higher orders and increase design complexity. The study also identifies a promising design space for CIFB modulators with high SR and low GBW, where advanced techniques like Slew Rate Enhancers (SREs) or comparator-based OTAs offer significant power savings despite challenges in achieving high resolution.
Currently, the demand for IoT devices is increasing. Among these, the sensor with low power consumption and small area is particularly important for power-limited, area-limited sensors such as in-body sensors. To achieve this, analog circuits, including passive components, can be eliminated as they are difficult to scale down and prevent performance improvement even with smaller technology nodes. Thus, we developed a compact, low power, high data rate, standard-cell-based passive-less wireless OOK transmitter. For this, we used a new circuit topology comprising duty controllers and pulse generator respectively consisting of five different delaying buffers and five NMOS transistors with different switch timings. The passive-less and digital-rich topology enabled the employment of scaled CMOS technology (12 nm FinFET). The chip area and energy consumption was reduced to 0.00027 mm(2) and 0.089 pJ/bit, respectively; the operational frequency and data rate increased to 41.6 GHz and 10 Gbps, respectively. Our study findings indicate further improvement along with technology scaling.
In 2019 we started to design RISC-V based ASICs including security IP with a focus on Post Quantum Cryptography (PQC) at our institute. The primary goal were small, resource efficient implementations with high flexibility through HW/SW-codesign. In a first ASIC we included tightly coupled PQC accelerators directly integrated in a 32 bit RISC-V processor. We achieved speedups and power savings of a factor 10 for many lattice based PQC algorithms. Furthermore, this design included HW-Trojans to demonstrate the risk of such attacks and to perform research on Trojan detection techniques. In a second ASIC we went for loosely coupled accelerators optimizing bus integration. We also included accelerators for isogeny based PQC and code based cryptography. Furthermore higher frequency and a smaller technology was used. The underlying idea was to get experience for chip design with the first tapeout on a 65 nm technology and use this for the second tapeout in a 22 nm technology with a more challenging design flow. The third step remained in the same technology but went from a simple RISCV platform to a complex security platform provided by the OpenTitan open-source project. The target here was to modify this platform in such a way that key storage can be achieved with Physical Unclonable Functions (PUFs) and PQC enhancements are included in the big number processor. With these ASICs we enable deeper security analysis of implementations in our hardware lab. The first chip was, e.g., given to a reverse engineering lab to reconstruct the netlist from the silicon and to find the Trojans. Additionally, the chip design activities educate students and PhD candidates addressing the needs of the industry in more skilled people.
High-performance simulation platforms are integral to advancing research in computational neuroscience. Recently, the development of multi-FPGA platforms for such simulations has gained prominence due to the inherent flexibility of FPGAs, allowing them to adapt to the evolving demands of computational neuroscience. These platforms have reached sub-realtime simulation capabilities for medium-sized models with realistic biological considerations. Despite leveraging communication architectures with minimized network diameter and traveling distance, further acceleration is constrained by the communication architecture, specifically the communication latency. This study addresses the latency bottleneck associated with inter-FPGA communication in computational neuroscience simulators. The serial interface and the accompanying communication protocol significantly contribute to this latency. The existing solutions optimize the protocol without considering their design impact on the interface latency, which must be considered when transferring a vast number of small packets - the typical traffic load in computational neuroscience simulators. To tackle this, we introduce a customized ultra-low latency serial link utilizing FPGA-embedded multi-gigabit transceivers. This design offers the flexibility to adapt to various application demands while minimizing latency by co-optimizing the physical and link layers. Experimental results on the Xilinx U200 platform demonstrate that a 128-bit packet can be transmitted from a router to a neighboring router over a 15.625 Gbps link in 34 ns. Our analyses show that employing the proposed customized link can lead to a 72-fold speedup in the neuroAIx platform when simulating the microcircuit model.
