Ferroelectric Tunnel Junction (FTJ) is an emerging non-volatile memory technology with increasing applications in storage and computing. The low programming energy of these devices make them an excellent candidate for low-power and power constrained applications. The multi-bit capability of these devices is exploited for Matrix Vector Multiplication in memory. To program the FTJ devices to multiple states, on-chip READ and WRITE circuits are necessary. In this work, we first present the programming circuit for multi-bit FTJ. Our circuit is able to generate pulse of two different amplitude from the input pulse and apply them across the FTJ. The READ circuit is able to convert the polarization state of the FTJ (which is represented in pA currents) to a CMOS-compatible voltage. The presented circuit occupies low area in addition to being energy-efficient. The presented circuits can be adapted for other NVMs and has a strong potential to find immense application in In-Memory Computing.
This brief presents a 10 Gb/s low-power single-ended linear equalizer for DRAM interfaces in 12nm FinFET technology. The proposed architecture consists of a continuous-time linear equalizer (CTLE) to compensate for the channel loss followed by a variable gain amplifier (VGA) to enhance the DC gain and sampling margin. The gain of the VGA is controlled by changing the source current, which can improve the power efficiency of the receiver based on the channel loss. Furthermore, another two common multi-stage equalizer approaches including two-stage CTLE and single-ended gain amplifier followed by a CTLE were designed and simulated in the same technology to compare with the proposed architecture. The simulation results show that the proposed linear equalizer exhibits the best overall performance in terms of power dissipation, area and eye height. The proposed equalizer consumes 0.94 mW at the Nyquist frequency of 5 GHz and 0.8 V supply voltage. It also compensates for a channel loss of 15 dB with a figure-of-merit (FoM) of 6.26 fJ/bit/dB, surpassing other previous works.
The Sets Of Real Numbers (SORN) format is a derivation of the universal numbers (unums) and represents an interval-based, low precision number format. It relies on lookup table (LUT) arithmetic, which can be implemented as ROM-like logic circuits. Previous works have evaluated the format for different use cases and applications, mostly under the assumption that the format can only be applied efficiently for bitwidths below 20 bit, because of the increasing complexity of the LUTs. This work evaluates on this assumption by implementing SORN addition and multiplication for different SORN datatypes and bitwidths between 5 and 31 bit, and comparing the resulting hardware circuits to standard integer implementations. The findings in this work show that SORN arithmetic actually scales quite well with bitwidth and mostly outperforms integer arithmetic in terms of hardware measures. Solely the area requirements of the SORN addition modules are higher than for integer designs of same bitwidth, whereas for multiplication a significant area reduction of up to 80% can be achieved. Further, the SORN modules are at least twice as fast as integer, and reduce the power consumption by up to 50% and 97% for addition and multiplication, respectively.
Application-specific instruction-set processors (ASIPs) can yield significantly better performance and energy efficiency results compared to general-purpose processors, while maintaining programmability. Instruction set customization raises the issue of how to integrate co-processors implementing custom instructions with the datapath, as using microarchitecture-specific interfaces lead to difficulties reusing them for other processors. Equally important is applying automatically retargeting compilation for the custom instructions to ensure easy utilization. To this end, we introduce a method for constructing an automatically retargeting compiler toolchain and a flow for generating Core-V eXtension interface compatible co-processors that can adapt to the same architecture description. We demonstrate the toolset by designing an ASIP based on the CVA6 processor for three BEEBS benchmark suite applications, which reduces the execution time 26% on average with an area overhead of 1% without affecting the clock frequency of the synthesized hardware implementation.
This paper describes a novel on-chip digital aging sensor circuit capable of detecting MOS transistors wearout due to negative-bias temperature instability (NBTI). The proposed aging sensor circuit enables us to identify the $V_{t h}$ shift of a pMOS transistor only from the sensing outputs without building simulation models or complex calibration procedures. To achieve this, the proposed circuit monitors the leakage-current based charge accumulation speed that is affected by a stressed pMOS power switch. We designed and implemented a test chip in a 65nm FDSOI CMOS technology. By operating the fabricated test chip at an ultra-low voltage (i.e. 0.3 V), we observed a clear linear relationship between the logarithm of the charge accumulation time and the reciprocal of the temperature, which is indicated in derived analytical expressions. From the slope value of the linear relationship, the rate of increase in ${V}_{t h}$ due to stress was successfully obtained. We also demonstrate that the proposed aging sensor circuit can detect aging at actual use at a nominal voltage.
