The rapid ascent of Artificial Intelligence (AI) is reshaping every facet of modern life; however, sustaining its transformative momentum demands a parallel evolution in design and test methodologies for AI hardware. This paper identifies three imperatives to enable future AI systems - scalability, sustainability, and trustworthiness. In discussing them, it explores the critical role that design and test innovations must play in meeting those demands. From addressing computational bottlenecks and environmental costs to ensuring secure, interpretable, and privacy-preserving AI, the manuscript highlights emerging challenges and promising solutions, including chiplet-based hardware, graph-based machine learning models, and secure execution technologies. Case studies such as the “ACRE” and “GLEAM” hardware accelerators demonstrate the power of hardware-software co-design to deliver scalable and efficient AI solutions. Ultimately, this manuscript calls for a coordinated response from academia, industry, and policymakers to build AI systems that are not only powerful, but also transparent, energy-conscious, and worthy of societal trust.
Analog compute-in-memory (CIM) engines perform multiply-and-accumulate (MAC) operations within the SRAM array. However, pitch-matching constraints limit the on-chip analog-to-digital converter (ADC) to approximately 7–8 bits, while AI workloads require up to 10-bit MAC precision. We present a subtract-mirror-amplify (SMA) residue amplifier, in-SRAM current-mirror calibration, and real-time process/voltage/temperature (PVT) correction that together extend a single 7-bit ADC to effective MAC precision of 2–10 bits, a range-mapped quantizer resolution reported alongside a measured analog-error statistic quantifying how closely it is realized in silicon. We also introduce fractional-range quantization (FRQ) and input-conditioned quantization (ICQ), which adapt output precision to each neural network layer’s requirements. A practical 424 Kb SRAM CIM macro with PVT calibration, in TSMC 28 nm, achieves 196.6–102 tera-operations per second per watt per bit (TOPS/W/b) across 2–10 bits of output precision, with under 1% accuracy loss on MNIST, CIFAR-10, CIFAR-100, and ImageNet.
The growing complexity of automotive semiconductor systems demands structured, scalable approaches to functional safety integration across intellectual property (IP) and system-on-chip (SoC) development boundaries. Processor IP plays a central role in realizing safety mechanisms that satisfy ISO 26262 requirements; however, integrating IP-level safety artifacts into SoC-level safety architectures introduces persistent challenges related to failure mode interpretation, safety responsibility allocation, diagnostic coverage reconciliation, timing consistency, and bidirectional traceability management. This paper introduces the Hierarchical Safety Artifact Propagation (HSAP) framework — a structured methodology that formalizes the transformation, reconciliation, and aggregation of safety artifacts across abstraction layers. HSAP defines a three-layer integration model comprising an IP-Level Safety Analysis Layer (HSAP-IP), a Structured Propagation Layer, and a SoC-Level Integration and Safety Aggregation Layer (HSAP-SoC). The framework explicitly models failure propagation pathways, coverage harmonization procedures, timing budget allocation, and bidirectional traceability generation to reduce integration ambiguity and improve overall safety case coherence. By systematizing artifact propagation across IP and SoC domains, HSAP provides actionable, implementation-oriented guidance for scalable functional safety integration in modern automotive semiconductor development environments.
