Understanding the structure and simplification of electrical circuits is a core skill in technical education. Yet, many students struggle with this, particularly for circuits in non-standard, non-intuitive schematic layouts. To bridge this gap, a key challenge lies in developing methods that can generate readable and pedagogically meaningful schematic diagrams from netlists. This paper introduces a graph-theoretical algorithm that transforms series-parallel netlists into consistent, human-readable schematics. By modeling circuits as directed multigraphs, the algorithm recursively identifies and reduces series and parallel substructures, reconstructing the schematic with clear, standardized layout rules. The resulting diagrams support students in recognizing structural patterns and reasoning through simplification steps. We evaluate the approach through a small-scale user study with university students and a complementary computational study using Multimodal Large Language Models. Both evaluations suggest improved performance for the standardized layouts. Our algorithm is integrated into simpliPFy.org, a web-based learning tool for electrical engineering that guides learners through the step-by-step simplification.
Silicon photonic integrated circuits are increasingly used in high-speed communication and emerging optical computing systems. However, fabrication process variations introduce deviations in waveguide dimensions, refractive index, and coupling parameters. These defects degrade device performance through resonance shifts, insertion loss variations, and phase errors. As silicon photonics moves toward large-scale integration and high-volume manufacturing, efficient testing methodologies are required to ensure device yield, performance, and reliability. This paper reviews testing strategies for silicon photonics, with an emphasis on the impact of fabrication process variations and associated degradation models. It summarizes state-of-the-art industrial test practices used for photonic devices and circuits, including wafer-level optical testing and design-for-test approaches. The paper also discusses the potential of data-driven and learning-based techniques for improving test efficiency and diagnostic capability. It highlights critical open challenges and outlines future research directions toward scalable and reliable testing of next-generation silicon photonic systems.
Reproducibility remains a major challenge in computational science and engineering, especially in electronic design automation, computer architecture, chip design, and hardware security, where legacy papers often depend on obsolete toolchains, missing code, unavailable platforms, and underspecified experiments. While LLMs and agentic AI can assess artifact adequacy or score papers against reproducibility checklists, this perspective argues that the underexplored frontier is GenAI as an automated reproduction engineer and benchmark builder. We propose a taxonomy of GenAI roles in reproducibility and focus on hardware domains, where GenAI may help reconstruct RTL designs, EDA flows, architecture simulators, and security artifacts. We frame the resulting ‘GenAI Reproduction Lab’ as a verification-centered workflow that accepts generated artifacts only through executable validation, provenance tracking, and expert review.
Interpolation filters are computationally intensive components in video encoding, essential for accurate motion estimation (ME) and motion compensation (MC), directly impacting coding efficiency. In the AV1 encoder, complexity increases due to adaptive filter selection based on video content, leading to high switching activity and challenges for energy-efficient hardware design. This work proposes DASH-AV1, a learning-based architecture that dynamically controls operand isolation during sub-pel interpolation. By analyzing real-time features from the encoding process, it predicts when filtering operations can be skipped with minimal quality loss. Experimental results show power savings up to 26.5% compared to a baseline, while maintaining coding efficiency.
The Internet of Things demands ultra-low-voltage RF receivers. Although low-noise transconductance amplifiers offer superior efficiency, their operation is sensitive to process, voltage, and temperature variations. This paper addresses challenges by presenting a robust circuit design methodology in 65-nm CMOS. We introduce a sizing approach based on lookup tables and a biasing metric. Furthermore, a hybrid active-biasing strategy employs two feedback loops. Post-layout simulations at 5.8-GHz demonstrate a gain of 9.07-dB, a noise figure of 4.16-dB, IIP3 of -0.76-dBm, and power consumption of 111.6-μW.
As device scaling has slowed at advanced process nodes, understanding real-silicon power behavior is critical for efficient server design. This article presents a consistent, measurement-based survey of ten generations of Intel Xeon server processors (32 nm–3 nm), quantifying how process scaling, voltage, and architectural evolution influence dynamic capacitance, non-core power, and overall performance-per-watt. The results provide empirical guidance for future design and validation flows that must balance energy efficiency, frequency, and power limits.
High Level Synthesis (HLS) has emerged as an industry de-facto standard in designing hardware accelerators and reusable intellectual property (IP) cores used in the system-on-chips (SoCs). However, the design process of HLS exposes critical security vulnerabilities in the form of backdoor hardware Trojan (HT). This paper presents a novel HLS-aided Trojan for register allocation tampering (RAT) attack, without affecting the functionality of the IP design. It introduces a new variant of HLS Trojan called ‘RAT-HT’ that can be secretly inserted by an HLS tool developer during datapath design stage for tampering register allocation information, also resulting into unwarranted power drainage. The proposed timer-sensitive HLS-aided RAT-HT attack is capable of inducing tampered register allocation as well as greater power drainage than prior works.
Unconnected input ports in RTL testbenches produce two distinct failure modes: visible X-propagation that triggers assertion storms, and silent functional hangs where zero tieoff eliminates X but leaves the design non-functional. This paper proposes a config-driven initialization flow combining lint-based detection, spec-first resolution, and LLM-assisted semantic inference as a fallback for undocumented ports. Per-port values are captured in a version-controlled YAML policy; specification-sourced values are applied deterministically, and all LLM-inferred values require explicit engineer approval before inclusion. The approach is validated on the Ibex RISC-V core [1] across three parameter configurations, PicoRV32 [11], and a UART peripheral [12] using an industry-standard RTL simulator. After mandatory engineer review and approval of every LLM-inferred value, config-driven initialization produced correct simulation outcomes in the evaluated cases. Three behavioral classes emerge: in the Ibex and UART cases, zero tie-off causes a silent functional failure despite eliminating X; in the PicoRV32 case, zero is safe but the YAML policy still documents the reasoning for future re-review; and open ports either fail immediately or remain latent when tests do not exercise the exposed interface. Correctness in every experiment is guaranteed by engineer review, not by the tier architecture alone. These results confirm the primary Ibex finding across multiple IP families and configurations. A cross-run consistency study across sessions and two LLM families shows where the base prompt fails and how refinement restores agreement on functionally significant ports.
Side-channel attacks exploit unintended information leakage (e.g., power, timing, sound, etc.) to extract sensitive data from electronic systems. Power-based side-channel attacks are most explored in the research community since there is a strong correlation between power consumption and the internal data processing. In this tutorial, we describe how to successfully attack embedded devices using power-based side-channel analysis. Specifically, we provide detailed steps in solving eight challenges from 2025 CSAW embedded security challenge. This article provides a hands-on tutorial for students, researchers, and practitioners, offering practical insight into side-channel attacks on modern embedded systems.
The Design, Automation, and Test in Europe (DATE) Conference reaffirms its role as a premier global forum for the electronic design automation and silicon design community to exchange ideas, present research advances, and seed innovation across academia and industry. Recently recognized as an “A” conference by the ICORE Conference Ranking, DATE brings together designers and design automation users, researchers, and vendors, as well as specialists in hardware and software design, test, manufacturing, embedded systems, and emerging computing technologies. The 29th edition of DATE was held in Verona, Italy, from 20 to 22 April 2026, continuing the interaction-centered three-day format developed and refined over recent editions.
Hardware Trojans (HTs) have largely been examined through a digital lens that assumes discrete signals, standardized test hooks, and golden references. Today’s systems-on-chips (SoCs) and systems-in-packages (SiPs) are inherently mixed-signal. Analog and RF blocks are indispensable for sensing, conditioning, power delivery, and communication; however, they expose attack surfaces that digital-centric taxonomies and tests miss. This article uncovers the overlooked analog/mixed-signal (AMS) threat space, explains why AMS HTs are attractive to adversaries (long lifecycles, limited fabrication diversity, compact single-function dies, and broad tolerances under process, voltage, and temperature variation), and distills the limitations of current detection, such as dependence on golden models, non-standardized analog test practices, and limited observability. We highlight shared-infrastructure channels (for example, supply rails), provide exemplar domains such as biometrics and communication, and draw practical implications for design, verification, and post-silicon test. We illustrate AMS HT and detection feasibility through three concise case studies, namely, harmonic-supply exfiltration, cross-domain ECG manipulation, and corner-aware disambiguation of PVT versus Trojan effects. Our aim is to motivate increased attention to analog-native and cross-domain HTs within mainstream design-and-test practices.
Chiplet-based heterogeneous integration enabled by wafer-level packaging and hybrid bonding is emerging as a practical alternative to continued monolithic SoC scaling. This approach allows many chiplets to be integrated with high-density die-to-die interconnects for improved performance, and a modular system design with smaller area and lower power consumption. However, these benefits come with sharply rising test cost and complexity, ranging from pre-bond screening to ensure known-good dies, to post-bond/package test to detect/locate assembly-induced defects, as well as in-field monitoring to ensure lifetime reliability. Manufacturing non-idealities such as die shift, warpage, misalignment, residue-induced shorts, opens, and coupling in dense multi-layer redistribution layers (RDLs) introduce defects that can span more than two chiplets and become difficult to excite and observe once interfaces are buried. This survey reviews recent state-of-the-art test methodologies for high-density many-chiplet packages, including test access fabrics and standard-based interfaces (e.g., UCIe/IEEE 1838), external testing versus built-in self-test strategies, physically aware pattern generation, scalable diagnosis, and RO/telemetry-based approaches for weak-defect sensing and lifecycle monitoring. We highlight academic research and industry practice aimed at efficient and effective field-aware test infrastructures for next-generation advanced packages.
Objective metrics for performance, power, and area are well established in digital hardware design. By contrast, metrics for implementation security, particularly for quantifying resistance to physical attacks, remain less unified and are often reported under varying assumptions, datasets, and threat models. This article surveys metrics used for two important classes of physical implementation attacks: side-channel analysis and fault-injection attacks. Rather than simply enumerating prior work, we organize existing metrics according to evaluation stage, including pre-silicon and post-silicon analysis, security objective, including leakage detection, exploitability estimation, localization, and countermeasure assessment, and attack model. This organization highlights four recurring challenges: (i) limited comparability across studies, (ii) weak support for early-stage design evaluation, (iii) ambiguity in interpreting attack-independent versus attack-based metrics, and (iv) less mature reporting practices for fault-injection attack evaluation. By examining side-channel analysis and fault-injection attack metrics together, this article identifies areas where current evaluation practices remain inconsistent or incomplete. Our goal is not to introduce another new metric, but to distill open research questions and lay a principled foundation upon which the community can build reliable and comparable security metrics.
Network-on-Chip (NoC)-based Manycore Systems-on-Chip (MCSoCs) are vulnerable to security threats, such as Hardware Trojans (HTs), which can manifest as difficult-to-detect anomalies in packets exchanged between communicating tasks. State-of-the-art detection methods typically fail to identify these anomalies or impose prohibitive hardware overhead. This paper proposes a lightweight, real-time, and non-invasive security framework that uses XGBoost to predict the temporal signatures of application traffic and detect anomalies. The methodology leverages clock-cycle-accurate simulations on a synthesizable MCSoC to generate realistic datasets that capture hardware-software interactions. To ensure scalability and minimal overhead, the framework employs an Observation-Decision-Actuation (ODA) management strategy and a transpiler to convert ML models into optimized, dependency-free C code for embedded execution. Experimental results across diverse benchmarks demonstrate sensitivity from 0.83 to 1.0 and F1-scores above 0.8. The system achieves real-time detection ranging from 52.6 μs to 60.4 μs, with a memory footprint of approximately 20 kB and a negligible impact on application execution time. These results show that the proposed software-based ML approach effectively identifies HT-induced anomalies without requiring modifications to the NoC routers.
Quantum computing has the potential to solve a wide variety of classically intractable problems. However, the inherent complexity, probabilistic behavior, and fragility of quantum systems pose significant challenges to ensuring the correctness and reliability of quantum programs. In this survey, we present a comprehensive overview of functional testing and validation techniques aimed at addressing these challenges for quantum circuits. We begin by outlining the unique characteristics of quantum systems that complicate traditional testing methodologies, including the absence of classical oracles, non-determinism due to quantum measurement, and the exponential growth of the state space. We then categorize and analyze a wide range of functional testing and validation techniques that have emerged to meet these challenges, including mutation testing, fuzz testing, and coverage testing. We further explore advanced semantic and white-box methods such as property-based testing, metamorphic testing, equivalence checking, fault testing, assertions, and concolic testing. Specifically, we discuss the applicability of these testing techniques to quantum circuits and examine their limitations in the current NISQ (Noisy Intermediate-Scale Quantum) era.
