We developed a new 1200-V reverse conducting insulated gate bipolar transistor with a structure called Schottky and multi-layered anode (a unique carrier injection control approach without lifetime-control) for TOYOTA's 5th generation hybrid electric vehicle and plug-in hybrid electric vehicle systems. The developed devices reduced total losses (conduction and switching losses) by 10% compared to the conventional product. It also reduced the number of parts for the power module and contributed to its 25% size reduction, ultimately contributing to the downsizing of 13% of the power control unit.
In this work, the low-loss reverse conduction and high threshold voltage characteristics are simultaneously demonstrated in 1 kV/10 A $p$ -GaN high electron mobility transistors (HEMTs) on an existing 6-inch process platform, thanks to the combined advantages of the uniquely designed source-controlled p-GaN hybrid structure and improved gate-stack layer. The reverse-conduction turn-on voltage of the resultant device is effectively decoupled from the threshold voltage and gate bias, which is different from the conventional p-GaN gate HEMTs. In addition, superior dynamic performances with nanosecond reverse recovery and switching characteristics are also realized, revealing the notable potentials of the high- $V_{\text{TH}}$ low-loss p-GaN HEMTs for high-power and high-frequency applications.
A novel structure named bipolar mode activation cell (BMA cell) is demonstrated to prevent current crowding in parallel connections of SBD-embedded SiC-MOSFETs during a surge current event. In a BMA cell, where the SBD area is partly filled with p-body to inactivate the corresponding part of SBD, I-V characteristics are uniform for each parallel-connected device under a surge condition. The parallel-connected devices with BMA cell have more than 5 times higher surge current capability compared with the conventional devices owing to the absence of current crowding.
A novel junction termination technique (JTT) is proposed, which combines three techniques of the optimum variation lateral doping (OPTVLD), buried-layer (BL) and high-k (HK). By utilizing the OPTVLD and BL techniques, an ideal electric field distribution is achieved, resulting in excellent cost-performance. Moreover, by adopting a SrTiO 3 film with high permittivity, which induces bound charges that respond automatically to the deviated charges, an extraordinary anti-charge-deviation ability is obtained for the first time. According to the simulation results, in comparison with the conventional JTT structure without the SrTiO 3 film, the proposed one gets better process windows increased by 93.3%, 73.9%, 73.9% and 61.3%, with respect to the deviation factors of dose, temperature, heating time and interface charge, respectively. Moreover, since the proposed JTT can be realized by BiCMOS-compatible process, it is budget-friendly and highly feasible.
This paper presents the development and evaluation of a 1.2 kV 4H-SiC Split-Gate (SG) MOSFET with a deep P-well structure that effectively reduces the maximum electric field in the gate oxide (Eox), increases the short-circuit withstand time (SCWT), and reduces the switching energy loss. Channeling implantation was implemented to achieve a deep junction with low implantation energy in the proposed SG-MOSFET. The conventional MOSFET, conventional SG-MOSFET, and proposed SG-MOSFET were successfully fabricated and evaluated. The measured static, dynamic, and short-circuit characteristics were compared. In addition, 2D simulations were conducted to support the experimental results and extract the electric field in the gate oxide. The proposed SG-MOSFET outperforms the conventional SG-MOSFET with a 1.06× increase in BV and a 1.78× decrease in E ox . Additionally, the proposed SG-MOSFET shows a 1.52× improvement in SCWT compared to the conventional SG-MOSFET. Further, the proposed SG-MOSFET enhances [Ron × C rss ] by 2.66× in comparison to the conventional SG-MOSFET, leading to the reduction of E off and E total by 1.5× and 1.05×, respectively.
