This work presents a Generalized Pulse-Swallow Frequency Divider (G-PSFD) architecture designed for dualmode operation in n255 and n256 Non-Terrestrial Network (NTN) frequency synthesizers. Unlike conventional frequency dividers constrained by fixed additive division laws, the proposed G-PSFD introduces a unified mathematical framework that supports both additive and subtractive division modes. This dual-mode flexibility enables the architecture to cover wide frequency offsets while minimizing hardware complexity. Notably, the subtractive mode reduces the swallow counter to only 2 bits, eliminating two flip-flop stages compared to conventional designs targeting the same n255/n256 NTN bands. To validate the model, the G-PSFD was integrated into a 1.5-2.2 GHz phase-locked loop (PLL) using a 32.768 MHz reference clock. Results demonstrate a maximum frequency error below 0.5% and lock times under $8 \mu \mathrm{s}$ with minimal control voltage ripple. The alignment between the analytical model and transient performance confirms that the G-PSFD provides the adaptability required for modern satelliteto-device communications while significantly reducing circuit complexity and logic overhead.
This work presents a gate driver in 180-nm CMOS SOI technology for SiC power MOSFETs. This technology is constrained by a maximum gate-to-source voltage of 5.5 V in both low and high voltages devices. To enable output swings from 15 V to −3 V, the proposed architecture employs multidomain level shifters while ensuring safe device operation. The design integrates voltage, current, and temperature protections for stable operation across worst-case PVT corners and elevated temperatures up to 144° C. Voltage protections include poweron reset (POR), under-voltage lockout (UVLO), and over-voltage protection (OVP) functions, while over-current protection is implemented with a DESAT circuit featuring a hysteretic comparator for robust fault detection and a programmable blanking time via a 3-bit selection cell. For temperature protection, a thermal shutdown circuit was implemented. The gate driver delivers peak currents up to 23.3 A and supports switching transients with $d v/d t$ exceeding $1.76 G V/s$, enabling compact and reliable high-voltage gate driving using low-voltage devices. Post-layout extracted simulations demonstrate robust performance during power-up, steady-state, and power-down conditions.
ECO-FMS (Energy Consumption Optimization through an Integrated LSTM-based Forecasting and Real-Time IoT Monitoring System) is an IoT-based solution developed to optimize energy management at the Raw Water Pumping Station (EEAB) Duas Unas, operated by Companhia Pernambucana de Saneamento (Compesa). The system combines real-time monitoring and AI-based multistep forecasting, integrating an IoT meter for voltage and current acquisition with a predictive model based on univariate and multivariate LSTM networks, enhanced by transfer learning, dataset concatenation, ensemble learning, and PSO optimization. The IoT meter achieved MAPE of 0.5% (voltage) and 1.1% (current), with 100% of measurements within a 5% error threshold. The predictive model forecasts 3-month energy consumption with accumulated errors of $\mathbf{1. 1 9 \%, 0. 4 8 \%}$, and 0.78%, achieving a 40% reduction in MAPE and a 360% increase in accuracy improvement over the baseline. Validation using an emulation environment confirmed the system's ability to measure, process, predict, and adapt to the facility's actual energy consumption of the EEAB Duas Unas.
The scaling of advanced CMOS technologies intensifies the impact of process variability on device electrical predictability and, consequently, on digital circuit performance. This article presents a comparative assessment between the predictive technologies ASAP5 (5 nm, GAAFET) and ASAP7 (7 nm, FinFET), using simulations in the HSPICE environment. Initially, $I_{\mathrm{D}}-V_{\mathrm{G}}$ curves were obtained and the DC metrics $I_{O N},\ I_{O F F}, V_{T H, H}, V_{T H, L}$, DIBL, and SS were extracted to establish a deterministic baseline. Next, a statistical analysis was carried out by means of Monte Carlo simulations at the device level, emphasizing the dispersion of $V_{T H}, I_{O N}$, and $I_{O F F}$ for NMOS and PMOS devices. Finally, a case study shows the propagation of variability through a NAND2 gate delay and power. Under nominal conditions, ASAP5 had improved electrostatic control, reflected in lower DIBL compared to ASAP7. The statistical analysis showed that $I_{O F F}$ is the metric most sensitive to variability, due to its exponential dependence in the subthreshold regime. At the circuit level, ASAP5 exhibited lower average power, but greater relative timing dispersion. The results reinforce the need to address process variability explicitly and hierarchically, from the device to the circuit level, in advanced CMOS design flows.
Deep Neural Networks (DNNs) have achieved remarkable success across diverse tasks, yet their deployment on edge devices is often constrained by significant computational and energy limitations. While input-dependent layer skipping offers efficiency gains, its stochastic routing introduces unpredictable execution times. This work proposes a contextual static inference framework that replaces dynamic gating networks with a library of pre-validated static skip masks. By utilizing Stochastic Depth (SD) training, we establish a functional resilience gap that enables arbitrary block skipping without performance collapse. Our methodology explores the design space of 218 configurations for a ResNet-38 architecture across CIFAR-10, CIFAR-100, and SVHN benchmarks. Experimental results demonstrate that at 50% execution depth, the resilient backbone sustains up to 89.7% accuracy with a ${1.73} \times$ speedup, whereas baseline models collapse to near-random performance. Furthermore, we show that optimal masks are data-dependent, allowing for contextual selection based on specific partitions. This approach ensures deterministic latency and zero decision overhead, providing a robust solution for inference in resource-constrained embedded platforms.
