Recent advancements in the space domain focus on integrating Artificial Intelligence (AI) solutions into safety-critical systems, necessitating highly dependable and interpretable AI due to the unique challenges of the demanding space environment, including stringent reliability requirements, constrained resources, and limited intervention capabilities, which, in turn, require increased transparency, explainability, and trust. This work provides an overview of the traditional challenges associated with deploying AI in space, emphasizing critical applications where elevated levels of trust are essential. We outline the classical requirements for trustworthy AI, linking them to emerging international legislative frameworks that aim to regulate this complex and evolving field. Furthermore, we consider an onboard anomaly detection use case and propose a novel design approach to provide an explainable AI solution. Our approach is intended to enhance the reliability of anomaly detection by leveraging both advanced AI techniques and conventional components of the onboard Fault Detection, Isolation and Recovery (FDIR) subsystem, while not significantly impacting on the required computational resources. Aligned with the principles of fault tolerance and system dependability, this special session aims to foster trust in autonomous AI technologies by promoting the development of high-performing, transparent, and accountable solutions essential for next-generation electronic systems.
Soft errors, typically caused by cosmic rays and particle strikes, have become a reliability challenge of modern electronics in aerospace, automotive, and high-performance computing. In advanced nodes with billions of transistors, a single strike can propagate errors, disrupting critical operations. As a result, traditional methods for estimating Soft Error Rate (SER), such as TCAD simulations and arithmetic formulas, are accurate but have become computationally expensive. In order to alleviate the computational burden, we propose a Model Order Reduction (MOR) approach to analyze charge collection dynamics induced by ionizing particles. More specifically, we start from the physics-based model of the diffusion-collection mechanism, then we discretize the fundamental equations in the 3D space, and formulate the system as a high-dimensional state-space problem. Finally, by applying the Extended Krylov Subspace (EKS) combined with Moment Matching (MM) techniques, we reduce computational overhead while maintaining accuracy. Experimental results demonstrate significant computational speedups while maintaining the accuracy of the full model.
This study examines the vulnerability of modern embedded GPUs—specifically the NVIDIA Jetson Orin NX and Xavier NX System-on-Modules (SoMs)—to Single-Event Effects (SEEs) under heavy ion irradiation. Originally developed for safety-critical environments such as automotive systems, these high-performance SoMs integrate advanced computing capabili-ties with built-in functional safety, positioning them as promising candidates for deployment in radiation-prone domains like space. We assess SEE behavior across various ion energy levels, focusing on the central System-on-Chip (SoC), which includes the CPU, GPU, and peripheral components. Our evaluation covers both the runtime and boot-time phases, providing a comprehensive view of fault susceptibility and its implications for system uptime and reliability in space conditions. The paper presents an in-depth analysis of error signatures observed in both the CPU and GPU due to ion strikes, contrasting these with outcomes from previous proton-based studies. Additionally, we compare the two NVIDIA platforms in terms of SEE types—including Single-Event Latch-up (SEL)—to evaluate their relative robustness and inform their potential adoption in space-grade applications.
In recent years, the increasing interest in space exploration has brought a significant change in the design of avionic systems. The growing complexity required a shift from using only low-performance, space-grade components to more performant Commercial Off-The-Shelf (COTS) components. These systems are, however, more susceptible to radiation-induced effects, and as such, require the engineers to implement advanced techniques of hardening-by-design or by software to increase the tolerance to Single Event Upset induced faults. Traditional scrubbing mechanisms for RAM with ECC encoding operate under the assumption that the entire memory space must be continuously checked for errors. However, this approach proves inefficient for complex space missions with varying mission scenarios, as it unnecessarily consumes resources by checking unused memory regions while potentially allowing errors to accumulate in critical areas. The need for more efficient error mitigation strategies becomes particularly crucial as space missions become more sophisticated and resource-constrained. This work proposes an innovative memory profiling-based scrubbing mechanism leveraging Hardware-Software Co-Design principles. Our approach introduces a specialized scrubber designed around the memory system, which interfaces with a register file accessible as a memory-mapped peripheral. The methodology involves a three-stage process: initial application compilation, memory profiling to determine occupation patterns, and application modification to program the register file with profiling results. This targeted approach ensures that only actively used memory regions are scrubbed, significantly improving efficiency while maintaining robust error protection in critical memory areas. The proposed solution offers a practical balance between system reliability and resource utilization, particularly valuable for modern space missions where optimizing both performance and radiation tolerance is essential.
As digital systems become increasingly integrated into radiation-prone environments, such as aerospace, automotive, and edge computing platforms, their ability to operate reliably under radiation-induced faults is essential. These faults, ranging from transient disruptions to permanent errors, can affect various system layers. In this work, we present an investigation into such challenges, combining simulation-based fault analysis with experimental validation. We introduce a novel methodology for modeling Single Event Transients (SETs) in clock distribution networks, enabling precise evaluation of Flip-Flop (FF) sensitivity. Additionally, a cross-layer framework is introduced to analyze how low-level hardware faults affect inference behavior in Dynamic Neural Networks (DyNNs), highlighting the unique reliability challenges posed by adaptive neural architectures. Finally, we present neutron irradiation results from a soft-core fault-tolerant RISC-V SoC implemented on an SRAM-based FPGA, revealing the critical role of architectural mitigation strategies for Single-Event Upsets (SEUs) and preserving system functionality.
