Nano-electro-mechanical circuits exhibit attractive resilience to radiation and high temperature, but suffer from wear-out. Previous studies have already proven that self-timed circuit design is a promising choice to extend their lifetime. This paper presents an exploration of different protocols and design styles on different sets of available NEM switch types as a foundation for identifying the most suitable choice.
Marino (IEEE ToC,1977) developed an equivalent circuit to describe the output behavior of a Schmitt Trigger. This beautifully simple model has proven specifically useful for investigating the metastable regions of this device. However, with its few and idealized analog components, it fails to reflect certain (metastable) behaviors of real-world Schmitt Trigger implementations. In this paper we augment Marino’s approach by amplifiers in the feedback- and in the input path to extend its modeling capabilities towards such behaviors. Our simulation results confirm the desired expressive power of our new model that not only allows to cover a wider range of observed Schmitt Trigger output characteristics, but also facilitates modeling additional related other circuits, e.g., the D-latch. The characterization effort is still low, relying on at most seven values that can be extracted from the (meta)stable states.
Several recent projects have proposed approaches to traffic engineering that schedule workloads to maximize the idle time of network equipment in order to reduce overall power consumption. However, today’s switches and network interface cards (NICs) consume significant power even while idle. This power inefficiency both increases operational costs and has a tremendous environmental impact. The key obstacle in realizing an energy proportional switch is physical link performance, i.e., creating a high-speed SERDES (serialization/deserialization) link.Asynchronous circuit designs, which do not rely on a global clock, make any digital computation energy proportional by their nature. However, asynchronous SERDES design is a relatively unexplored topic. In this paper, we improve on a previous SERDES design to incorporate continuous-time equalization hardware and circuit-level optimizations for the digital processing that takes the data rate to 20 Gbps in a 65nm technology. Through circuit simulation, we demonstrate that the SERDES link is energy proportional. Overall, this is an important step towards designing energy-proportional network switches and NICs.
Flexible integrated circuits (FlexICs) fabricated on metal-oxide thin-film transistor processes suffer from substantial process variability, making asynchronous design an attractive approach: self-timed circuits adapt to actual gate delays rather than relying on worst-case timing margins. Validating such circuits at wafer scale, however, requires test infrastructure capable of exercising delay-insensitive handshake protocols, detecting per-channel faults, and capturing timestamped signal traces across thousands of die sites. This paper presents an FPGA-based testbench for automated wafer-level testing of asynchronous FlexICs synthesised with the ALHO self-timed template. The testbench implements the full four-phase dual-rail handshake protocol, provides per-channel timeout-based fault detection, in-hardware golden-result verification, and cycle-accurate event capture. A backpressure mechanism freezes the handshake controller when the event buffer fills, preventing data loss without requiring oversized FIFOs. The same infrastructure supports a synchronous variant of the same classifier design, enabling direct comparison of yield and maximum operating frequency across design styles. The complete system integrates FPGA control with automated wafer stepping, source-measure unit power sequencing, and probe-card touchdown verification for unattended full-wafer characterisation runs.
Asynchronous circuits offer potential advantages in low power and performance. To design reliable asynchronous circuits, the Design-for-Testability (DfT) is essential, since it enhances fault detection, reduces test costs, and improves yield and reliability. However, there is no automatic test pattern generation (ATPG) method for the DfT architecture of bundled-data circuits, and manual test pattern generation is impractical for large-scale asynchronous circuits. To solve this problem, we propose a graph-based ATPG method for the asynchronous DfT architecture (A-ATPG) to detect stuck-at, at-speed, and bubble faults. We verify the proposed DfT architecture and A-ATPG method on asynchronous Fork-Join, Fibonacci, greatest common divisor circuits, an asynchronous RISC-V-based spiking neural network (SNN) processor, and an asynchronous Network-on-Chip (NoC) circuit, respectively. Experimental results show that the stuck-at fault coverage achieves over 99%, bubble fault and at-speed fault testing cover all paths across multiple test cycles. The RISC-V-based SNN processor and the NoC circuit show a 0.6% and 12.7% area overhead, and 5.3% and 9.2% power overhead with the DfT architecture, respectively.
