Hardware verification is a critical stage in the design flow, ensuring functional correctness and reliability of increasingly complex systems. Traditional verification methodologies, such as simulation- and formal-based approaches, suffer from limited scalability, high manual effort, and growing state-space explosion as design complexity increases. Recent advances in large language models (LLMs) have enabled their adoption for verification-related tasks such as testbench generation, assertions, security properties, and bug localization. However, existing LLMbased verification flows face significant limitations, including context-size constraints, lack of reasoning, and poor scalability across abstraction levels. To address these challenges, agentic workflows have emerged as a promising paradigm that orchestrates LLMs through structured reasoning, interfacing with toolflows and feedback loops. In this work, we provide a systematic assessment of current agentic LLM workflows for hardware verification, analyzing their practicality and limitations. Furthermore, we propose a novel LLM-based agentic framework that enhances verification effectiveness across RTL and gatelevel abstractions. We demonstrate the potential of the proposed frameworks through evaluation on six open-source benchmarks, showing accuracy, coverage and speedup improvements.
Recent advancements in Large Language Models (LLMs) have demonstrated their growing capability to generate complex Register-Transfer Level (RTL) designs, including hardware accelerators for Post-Quantum Cryptography (PQC) primitives. However, hardware implementations of cryptographic algorithms demand more than just functional correctness and optimal performance; they must also offer resilience against sidechannel attacks (SCAs). For the first time in the literature, we explore the potential of LLMs to automate the generation of SCA-resilient RTL. We focus on the Number Theoretic Transform (NTT) operation in CRYSTALS-Kyber NIST standard for MLKEM, a critical cryptographic component known to be vulnerable to SCAs, mainly because of the constrained sample space of the key parameters used in these algorithms. By guiding the LLM to incorporate countermeasures during the design phase, this study aims to streamline the development of secure, next-generation cryptographic hardware.
Content-addressable memory (CAM), through supporting massively parallel search, holds great promise for many data-intensive applications, such as information retrieval, anomaly detection, and genomics. Motivated by multi-level cell (MLC) capabilities of emerging memory devices, recent advances in circuit and architecture design of CAM have explored analog CAMs (ACAMs) and multi-bit CAMs (MCAMs), opening new frontiers for improving storage density and energy efficiency, as well as enabling emerging applications. A significant challenge in designing ACAM/MCAM lies in managing inherent device and circuit non-idealities, which can inadvertently degrade application-level accuracy. This paper presents several representative ACAM and MCAM circuit and architecture designs based on different emerging memory devices, including resistive RAM, ferroelectric FETs, and Flash memory. Innovative device- and circuit-level techniques for mitigating the negative impact of these non-idealities are discussed. Furthermore, hardware-algorithm codesign approaches for enhancing overall system robustness are illustrated through accelerating two representative applications. Finally, a general CAM evaluation framework will be discussed with special emphasis on predicting the impact of the device and circuit non-idealities on application-level accuracy.
As large language models (LLMs) are increasingly fine-tuned for hardware tasks like RTL code generation, the scarcity of high-quality datasets often leads to the use of rapidly assembled or generated training data. These datasets frequently lack security verification and are highly susceptible to data poisoning attacks. Such poisoning can cause models to generate syntactically valid but insecure hardware modules that bypass standard functionality checks. To address this, we present SafeTune, a framework designed to harden LLM-based RTL generation against poisoning, specifically focusing on hardware Trojan (HT) insertion. SafeTune integrates two core components: (i) a Graph Neural Network (GNN) that models structural properties to identify anomalous circuitry patterns during fine-tuning, and (ii) a semantic verification module using text embeddings and an XGBoost classifier to assess prompt security. By coupling structural and semantic knowledge, SafeTune effectively filters poisoned inputs without sacrificing legitimate data. Experimental results demonstrate that SafeTune significantly enhances the robustness and reliability of LLM fine-tuning without requiring modifications to the underlying model architecture.
SystemVerilog Assertions (SVA) are essential for formal verification of digital hardware, yet their manual creation demands significant expertise in both the design under verification and temporal logic. Recent studies have explored using large language models (LLMs) to automate SVA generation, but existing approaches suffer from incorrect signal references, missing timing constraints, and lack of formal correctness guarantees. This paper presents ProofLoop, a tool-augmented ReAct agent that generates SVA from natural-language specifications using a solver-in-the-loop approach. The agent operates in two phases: Phase A autonomously gathers design context by invoking EDA and formal tools, including semantic search over an AST-indexed vector database and JasperGold structural queries, while Phase B generates SVA and iteratively refines it using JasperGold formal proof feedback over up to fixed (here 3) verification rounds. We evaluate ProofLoop on FVEval Design2SVA design benchmarks and demonstrate that this framework can achieve 93.7
