This paper presents an integrated IR-Informed Timing and Timing-Aware IR Optimization flow with an IR-drop predictor. The proposed flow couples an IR-Informed Timing Optimizer with a Timing-Aware IR Optimizer to consider the mutual impact between IR-drop and timing during optimization. Then, we leverage a fast ML-based IR-drop predictor to quickly estimate the IR-drop after each iteration of optimization, which enables fast switching between the IR optimizer and timing optimizer. We further propose Feature Approximation to speed up the inference time of the IR-drop predictor. On two 7nm designs, the proposed flow closes timing and eliminates at least 90.6% of IR-drop violations. The Feature Approximation achieves 67% speed up in the runtime of the overall flow. Our optimization flow can be applied to a 945k-cell design with 7,578 IR-drop violations within 3 hours, demonstrating its practicality.
Dynamic Deep Neural Networks (D2NNs) with early exits have emerged as an effective architecture for reducing computational overhead and inference latency. While fault tolerance in their static counterparts has been extensively studied, the dynamic models remain largely unexplored for enhanced reliability. This paper addresses that gap by developing Bayesian optimization algorithms to determine optimal early-exit confidence thresholds for enhanced fault resilience in dynamic DNNs. We present a reliability assessment of BranchyNet models compared to their static counterparts across three state-of-the-art architectures, introducing random bit flips (up to 0.01% of total model parameters) across 11 logarithmically increasing Bit Error Rates (BERs). The study analyzes fixed and adaptive thresholds that dynamically adjust considering the estimated fault rates. The results demonstrate that BranchyNet models exhibit greater fault resilience, preserving accuracy even at BER levels up to 2x higher than those tolerated by static models, with adaptive thresholds providing the strongest resilience. By combining exit threshold tuning with multiple inference pathways, early-exit DNNs offer a practical means to mitigate radiation-induced soft errors in hardware deployments.
Stochastic computing (SC) is an approximate computing that represents numerical values based on the probability of ones in bitstreams and performs operations probabilistically. Arithmetic circuits for SC (SC circuits) have attracted attention for applications such as machine learning and image processing due to advantages like not only low area and power consumption but also high fault tolerance. To accelerate stochastic computing based on linear finite state machines (FSMs), parallel implementation of linear FSMs has been proposed. The first objective of this paper is to analyze this parallel implementation method and to clarify the details of the design and the cost-effectiveness of the parallel implementation. Through this analysis, it is shown that hardware cost can be significantly reduced while maintaining high accuracy. As the second objective, this paper proposes a new method of parallel implementation using multi-input linear FSMs in order to further improve the accuracy. Experimental results show these proposed designs can achieve high accuracy while keeping the area and delay low.
Static learning has been used to improve structural Automatic Test Pattern Generation (ATPG) results by reducing backtracks and thus aborted faults. However, static learning is limited to simple relationships and can generate massive learning data, most of which is not needed during ATPG. We present a new dynamic learning technique to learn only needed relationships that can include multiple gates and time frames. We show improved coverage and pattern count on industrial design.
As the demand for Semiconductor Devices used in varied applications, such as consumer electronics to automotive, to aerospace, increases exponentially, more and more silicon wafers and packaged chips need to be tested before delivery. The key role of testing is to ensure that the semiconductor devices are free from any defects and meet all the required specifications before they are shipped to the customers. Contact resistance variability can create inaccurate test results, false failures, increase test time and yield losses. The need for compensating resistance variability will provide accurate test results with improved yield and test time, thus reducing the cost of semiconductor testing. This resistance calibration technique measures the resistance variability in the path from the ATE pogo pins to the device pins, which also includes contact resistance of the probe needles, by forming a Kelvin Connection using the device’s internal DFT, eliminating the need for special design requirements. The method has proven to improve yield by 1.25% tested on a 12-inch wafer with 12638 devices.
