True random number generators (TRNGs) perform an extremely critical role in cryptographic algorithms and security protocols, scientific simulation, industrial testing, privacy protection, and numerous other domains. Nevertheless, modern TRNGs have difficulty striking a reasonable balance between high throughput and low hardware consumption. In this paper, a novel lightweight high-throughput TRNG based on state switchable ring oscillators (SSROs) is proposed. Under the effect of flip-flops that are prone to entering the metastable region, the SSROs randomly switch between oscillatory and buffer states to create jitter and metastability. A feedback strategy is adopted to effectively eliminate the fixed point in the circuit, which further enhances the randomness of the structure. The proposed TRNG is implemented on Xilinx Artix-7 and Kintex-7 FPGAs, with support for automatic routing. It achieves a throughput of up to 400 Mbps while consuming only 16 LUTs and 13 DFFs, showing extremely high resource utilization efficiency. Experimental results show that the output random sequence passes the NIST SP800-22 test, the NIST SP800-90B test, and the AIS-31 test without any postprocessing, exhibiting strong robustness against voltage and temperature variations as well as frequency injection attacks.

True random number generators have broad application prospects in the fields of hardware and information security. In order to improve the throughput of true random number generator with lower hardware overhead, an autonomous Boolean network with coupled basic logic units and imbalanced node oscillating rings is constructed as the entropy source. A first-order high-frequency oscillation loop is used to enhance the network refresh frequency, and a high entropy chaotic signal is generated through multi-level nonlinear coupling and amplification of the node output signals. Each output signal of the entropy circuit is sampled with D Flip-Flop and the result is sent to a post-processing circuit composed of XOR network, where the true random number is obtained. The proposed TRNG is implemented on Xilinx A7 FPGA development board. The sampled output data is grabbed and extracted in real time using the ChipScope IP module, and then transferred to computer for experimental testing. NIST SP800-22 and SP800-90B randomness tests are performed on the generated data, and some other important performances such as deviation, autocorrelation, and maximum Lyapunov exponent are also evaluated. The results show that at a throughput of 750Mbps, the proposed TRNG can generate true random numbers with entropy values of 0.996323bps, low deviation and low autocorrelation, being also of low hardware overhead.

Objective Logic testing using Automatic Test Equipment(ATE)is a critical step in integrated circuit(IC)manufacturing test to ensure chip quality.Enhancing logic test efficiency is essential to reducing digital IC testing costs.During testing,IC test data are typically stored in the main memory of the ATE user board and sequentially read to generate channel test waveforms.The time required to read test data directly affects test efficiency.Traditional Test Data Compression(TDC)approaches,which often require preprocessing such as X-bit filling,are suited only for scan testing and thus do not meet broader test engineering needs.Meanwhile,advances in Field-Programmable Gate Array(FPGA)technology have enabled the customization of high-speed Block RAM(BRAM)resources.This study proposes a test vector coding scheme based on component statistics,in which the Device Under Test(DUT)test vectors are encoded and corresponding component coding tables are generated and stored in the FPGA BRAM.A table lookup circuit is implemented to achieve synchronous,parallel output of all test vector components,effectively reducing the external data read time and improving logic test efficiency. Methods Each bit symbol in an IC test vector comprises four components:drive(DC),measurement(MC),high impedance(ZC),and residual value(RV).The proposed scheme performs statistical encoding of each component across all bit symbols in the DUT's test vectors and generates shared DC,MC,and ZC coding tables.The encoding process includes:(1)scanning and extracting each vector from the DUT test project files;(2)determining the bit component values and residual values for all channels;(3)for each component,compiling and deduplicating all generated codes,reassigning deleted code references to reserved codes to form the final coding tables;and(4)determining the combined component addresses and residual values.Using a Xilinx Kintex-7 FPGA development board and the Vivado tool,three BRAM modules are configured,and a BRAM table lookup control circuit is designed(Fig.4).Prior to testing,the component coding tables are downloaded to the FPGA BRAM,and the combined address and residual values of the three component codes for each test vector are stored in off-chip SDRAM.During operation,the lookup circuit uses the combined address to synchronously and in parallel output the three components,which—together with the residual value,drive the waveform generator to produce the channel test waveform. Results and Discussions The functionality of the BRAM-segmented synchronous table lookup circuit is verified through simulation.Three BRAM modules with 64-bit width and customized segment address depth are configured.The COE files of the component encoding tables are downloaded to the target BRAMs via a UART interface,using address generation control logic.The corresponding addresses are then applied to the lookup circuit.A complete simulation is conducted by integrating the segmented lookup module,data strobe module,address allocation module,and data transmission module,enabling validation of the BRAM data download,segmented table lookup,and I/O processes within the FPGA(Fig.6-Fig.8).Results confirm that the synchronized parallel output from the lookup circuit matches the three component codes of the predefined test vectors(Fig.9-Fig.13).The SDRAM read time is also analyzed.Under the same configuration parameters,the proposed encoding scheme reduces the read time of each test vector by 66.7％compared with a direct encoding storage scheme(Table 3),indicating a significant improvement in logic test efficiency.A qualitative comparison with traditional TDC schemes—including dictionary coding,Frequency-Directed Run-length(FDR)coding and run-length coding,is presented in Table 4.The results indicate that the proposed scheme,which utilizes high-speed BRAM embedded in modern FPGAs,supports non-scan parallel logic testing with high decoding speed and low overhead,while fully satisfying the original test project requirements. Conclusions A test vector encoding and decoding scheme based on component statistics and BRAM-segmented synchronous table lookup is proposed and implemented.The segmented lookup circuit is designed,and its functional correctness is verified through simulation.Compared with direct encoding,the proposed scheme achieves a 66.7％reduction in logic test time.In contrast to traditional TDC approaches,it offers lower hardware overhead by leveraging embedded high-speed BRAM.The scheme supports ATE-based parallel non-scan logic testing and meets the original engineering design goals,providing a practical foundation for optimizing the logic test function module of the ATE user board.

With the ongoing trend of reducing transistor size, dealing with self-heating effect (SHE) has emerged as a crucial challenge in ensuring the reliability of small-sized transistors. Accurately characterizing SHE is fundamental for predicting reliability. In this article, we focus on characterizing SHE in 14 nm finned field-effect-transistor (FinFET) by establishing the relationship between gate source voltage (V-GS), threshold voltage (V-TH), and SHE temperature (T-SHE). The model established in the article allows for SHE characterization of 14 nm nFinFET within a voltage range of 0-0.7 V (R-2 goodness of fit >99.95%; R Correlation coefficient >99.95%; error <1 degrees C) and 14 nm pFinFET within a voltage range of -0.3 -0.7 V (R-2 goodness of fit >99.95%; R Correlation coefficient >99.95%; error <1 degrees C), respectively. Simulation results further validates the applicability of our characterization method for 10 nm and 7 nm process technologies. Finally, a comparison of the characterization method with other methods reveals that the characterization method stands out for its broad applicability and streamlined steps, offering a solid methodological foundation for predicting SHE.

Due to the immaturity of the manufacturing process, numerous faults often occur in through-silicon vias (TSVs). Prebond TSV testing is crucial in enhancing the performance and yield of chiplet-based integrated chips. However, most existing test methods suffer from the test resolution and hard-to-detect weak faults. A novel prebond TSV test method based on the pulse is proposed to improve the test circuit. By introducing pMOS as a driver in pulse detection, TSV leakage faults can be directly tested, thus improving the resolution of leakage faults' detection. In addition, the range of test pulsewidth to digital code conversion is effectively improved by the ring oscillator (RO) for coarse detection and pulse shrinking for fine detection, avoiding the problem of large overheads that would be brought about by solely increasing the pulse shrinking chain. The results validated by HSPICE simulation show that it can detect open faults, resistive open faults with R-open > 0.9 K Omega, leakage faults with R-leak < 30 G Omega, and compound faults consisting of resistive open faults and leakage faults.

The ever-increasing complexity of integrated circuits inevitably leads to high chip test cost. Machine learning techniques can predict chip quality with a small number of test items, but require a similar number of passed and failed chips in the training data. Training a model with high yield chip data results in a large number of test escapes. In order to reduce the test cost and maintain the recognition rate of failed chips, an adaptive testing method based on ensemble learning is proposed. The degree of imbalance in the test data is alleviated by undersampling, and then the test items are filtered based on the model classification effects. Finally, to prevent imbalanced data from disturbing the ensemble learning algorithm, boundary adjustment is used to reduce test escapes. Experimental results using fabricated chips test data show that the proposed method reduces more than 34 % of test items in the face of high yield chips, and the accuracy of the classification of failed chips reaches more than 99 %.

The growing complexity of integrated circuits (ICs) brings expensive manufacturing test cost. Adaptive testing becomes an important way to save test cost by predicting die quality to reduce the actual test content. However, reducing test items often results in unacceptable levels of test quality degradation. An adaptive testing method is proposed in the paper to reduce test cost while guaranteeing test quality. Two quality predictors are trained with a subset of test items and spatial information for subsequent decisions. The dies are clustered according to the prediction results, and the clustering results are graded. The distribution of the different grade classes determines the die quality of each grade. Experimental results using fabricated wafers and the associated test data show that the proposed method reduces more than 42% of test items, and can achieve better test quality, reducing test escapes and yield losses by more than 90% in the Circuit Probing test (CP).

Analysis and prediction of self-heating effect (SHE) network modeling are important elements in nano-device research. This paper carries out SHE network modeling and analysis for 14nm finned field-effect-transistor (FinFET) devices and proposes a new model that improves the accuracy of SHE network through structural division and theoretical calculation. For the input power dissipation of the devices, a new formula is established to calculate the power dissipation of their grid cell. To calculate thermal resistance of such devices, a single discrete grid element is formed. Based on the calculation results of thermal resistance and power dissipation acquired from the theoretical formula, the temperature distribution across different regions of FinFET is obtained. The proposed model accurately simulated the temperature within devices and reduced the complexity temperature rise calculation of SHE. In addition, this model provides a basis for circuit design as well as a reference for discovery of potential defects.

Weak resistive defects in standard cells exhibit subtle electrical behaviour that may lead to test escapes, thereby compromising the reliability of integrated circuits. Fault analysis data has shown that the presence of weak defects in specific cells can cause variations in output timing when multiple transitions occur on the inputs, as opposed to a single transition. However, existing delay test generation tools do not account for the effect of multiple input switching (MIS). In this paper, the effects of MIS on defect detection and timing analysis are analyzed and a multi - transition delay test method is proposed to further expose and detect cell internal defects. In addition to sensitizing the selected paths, the new test pattern attempts to maximize the off - path input transitions, thus increasing the propagation delay of the selected paths or the proportion of incremental delay introduced by the defects. The simulation results on ISCAS benchmark circuits show that the proposed method achieves a maximum of 8.73% and an average of 5.99% defect coverage gain compared to the existing delay tests that based on single input switching schemes.

True random number generators (TRNGs) perform an irreplaceable role in securing information systems. In this brief, a lightweight hybrid entropy source TRNG implementation scheme based on jitter and metastability is proposed, which uses the underlying field programmable gate array (FPGA) primitive language to construct a dual cross-coupled XOR gate (DCCX) unit to generate a random output sequence and is deployed by automatic layout and routing with the Xilinx compiler. The experimental results show that the generated random sequence passes the NIST SP800-22 test, the TESTU01 test and the AIS-31 test. The structure has been extensively tested under voltage and temperature variations and shows excellent robustness. It is worth mentioning that the proposed TRNG consumes only 12 LUTs and 10 DFFs, and achieves 150Mbps and 200Mbps throughput on Xilinx Artix-7 and Kintex-7 FPGAs, respectively, which shows a highly efficient resource utilization compared to the previously published TRNGs.

The characterization of the self-heating effect (SHE) has been an important research topic in advanced technology, but the existing characterizations are few and the characterization process is relatively complex. In this research, a SHE characterization model is established based on the relationship between output transconductance variation (∆gm), gate source voltage (VGS) and temperature variation (∆T) caused by SHE through machine learning, and then the model is validated by theoretical analyses and experimental simulation. The characterization model is capable of directly calculating the ∆T caused by SHE during I - V testing and simplifying the SHE characterization steps while ensuring characterization accuracy (∆T difference < 1 °C), thus saving costs. It is also found that the model can expand the characterization range (VGS: 0.3–0.7 V) of SHE and conducts quantitative characterization with model calculation under different VGS, realizing a high characterization resolution of VGS: 0.01 V. The circuit level application proves that the method can be effectively applied to the characterization of the SHE and solves the problem of the characterization of the circuit level SHE.

With the introduction of FinFET transistors, the self-heating effect (SHE) became a major reliability challenge. This leads to accelerated defect generation and, if not considered carefully, a profound risk to integrated circuit (IC) reliability. In this article, simulation is used to analyze the SHE of 6T static random access memory (SRAM) based on 14-nm FinFET, providing a basis for the thermal layout of 6T SRAM in circuit design. The impact of SHE on 6T SRAM is analyzed. For the first time, it is proposed that the reading delay time with the change of duty cycle shows a rising and falling trend, which is further verified by using simulation, theoretical analysis, and field-programmable gate array (FPGA) experiments. Thus, the duty cycle and read delay time are utilized to achieve binary encoding for the characterization of the SHE of 6T SRAM. The results indicate that the method can be used to characterize the T-SHE,T-max (the highest TSHE among six transistors) range: 0 (degrees) C-84.5 C-degrees , with a T-SHE,T-circuit (representing T-SHE of the 6T SRAM) range: 0 C-degrees -48.8( degrees) C. The characterization method enables the practical measurement of SHE in circuits based on 6T SRAM technology, which is no longer limited to existing transistor simulation and modeling methods, allowing for more precise testing of circuit reliability. At the same time, it eliminates the need for additional thermal sensing circuits and testing equipment.

Unpredictable true random numbers are required in security technology fields such as information encryption, key generation, mask generation for anti-side-channel analysis, algorithm initialization, and so on. At present, the true random number generator (TRNG) is not enough to provide fast random bits by low-speed bits generation. Therefore, it is necessary to design a faster TRNG. This work presents an ultra-compact TRNG with high throughput based on a novel extendable dual-ring oscillator (DRO). Owing to multiple bits output per cycle in DRO can be used to obtain the original random sequence, the proposed DRO achieves a maximum resource utilization to build a more efficient TRNG, compared with the conventional TRNG system based on ring oscillator (RO), which only has a single output and needs to build multiple groups of ring oscillators. TRNG based on the 2-bit DRO and its 8-bit derivative structure has been verified on Xilinx Artix-7 and Kintex-7 FPGA under the automatic layout and routing and has achieved a throughput of 550 Mbps and 1,100 Mbps, respectively. Moreover, in terms of throughput performance over operating frequency, hardware consumption, and entropy, the proposed scheme has obvious advantages. Finally, the generated sequences show good randomness in the test of NIST SP800-22 and Dieharder test suite and pass the entropy estimation test kit NIST SP800-90B and AIS-31.

针对包交换片上网络(NoC)在大量数据通信情况下性能较差的弱点,提出了一种基于"包-电路"(PCC)交换的环形拓扑结构片上网络(DRNoC)设计架构.首先这种双环形拓扑结构由内外两环构成,可实现环内或环间双向通信,环上节点数目可拓展.其次DRNoC路由器通道可配置为桥节点或环节点路由器两种类型,相比于2D-Mesh型通道数减少,结构更加简单,资源消耗更少.最后提出了针对DRNoC的双环动态路由算法(DDRA),该算法无需在每个路由节点都进行输出方向的译码判断,在头包建立受阻时,根据网络情况选择其他路由路径,最大程度保证数据同环传输基础上跨环传输,有降低头包建立的等待时间,提高吞吐率.实验表明,在大量数据通信情况下,搭载DDRA算法的DRNoC的硬件资源开销降低的同时能够降低网络平均包延时提升平均吞吐率,有效地改善了网络性能.

In order to reduce the test cost and improve the test quality in ICs. A wafer-level adaptive test method with low test escapes is proposed. The method reduces the test cost of wafers to be tested by filtering the test set based on the effectiveness of the test item to detect faulty die in historical test data. At the same time, the degree of fluctuation of the parameters in the neighborhood of the die is analyzed, and the parameter differences of the die with fluctuations are amplified and modeled to improve the classification accuracy of the quality prediction model for this type of dies; the dies without fluctuations are used for quality prediction using the valid test set modeling method to reduce the risk of test escapes. Experimental results based on actual wafer production data show that the method can significantly reduce the test item cost of wafers by 40.13% and maintain a low test escape rate of 0.0091%.

With the rapid development of the Internet of Things, terminal equipment is greatly restricted in hardware resources and power supply. Therefore, there is an urgent need for new low-power computing units. Aiming at the problem of high power consumption of the arithmetic unit, a low-power approximate Booth multiplier based on complementary error is proposed. Among them, the new Booth encoder will produce positive errors and the approximate Wallace tree structure will produce negative errors. The mutual compensation of the two errors can improve the accuracy of the approximate Booth multiplier to a certain extent. The experimental results show that, compared with the existing multipliers, the proposed approximate Booth multiplier reduces the power consumption by 20.62% and the delay by 14.45%, saving 19.68% of the area. At the same time, its normalized average error distance is better than the existing approximate multiplier. Finally, the results of image filtering verify the practicality of the proposed approximate Booth multiplier.

集成电路飞速发展对集成电路自动测试设备(ATE)中时间测量单元(TMU)的精度提出了更高的要求.针对这一问题,本文使用电子学引脚测试芯片MAX9979对数字IC施加激励和捕获响应,结合Xilinx Artix-7 FPGA内部固化的时间数字转换器(TDC)设计了一种高精度的时间测量单元.时间数字转换器采用粗、细计数结合的内插方法,粗计数由参考时钟为200 MHz的32位直接计数器实现;细计数由超前快速进位链(CARRY4)级联的延迟链构成,通过对CARRY4进行专用配置来减小其超前进位功能引起的测量误差,使用码密度校准法对延迟链进行校准.实验结果表明,TMU量程为21.475 s,平均分辨率为 34.7 ps,DNL 优于 2.5 LSB,INL 优于 4.5 LSB,精度为 39.7 ps.

Advances in integrated circuit process technology have led to new defect mechanisms, and weak resistive defects in standard cells have received attention in addition to traditional defect types. Such defects are categorized as small delay defects that affect the reliability of a circuit. The delay introduced by such defects overlaps with the delay distribution resulting from the random process variation. Combining the results of the theoretical analysis, we propose a test method to improve the probability of detecting cell internal weak defects in the presence of process variation. The path with the minimum logic depth is selected as the test path, and the test pattern that enhanced the small delay of weak defects is paired with the test path. The improvements in defect detection probability over traditional tests are demonstrated on the ISCAS89 benchmark circuits. The results show that the proposed method provides an order of magnitude improvement in the probability of detecting cell internal weak defects.

Circuit delays are increasingly sensitive to process, voltage, temperature, and aging (PVTA) variations, severely impacting circuit performance. Accurate measurement of circuit delay is essential. However, the additional hardware structures for measuring circuit delay add to the critical path delay. To address this issue, this paper proposes a bypass-based ring oscillator (BPath-RO) that reduces the impact on the critical path delay by moving the added measurement control structures to the bypass. The proposed measurement scheme requires only two transistors inserted into the critical path, which is more conducive to engineering change order (ECO). Measurement simulation experiments were performed on representative critical paths of the ISCAS’89 s298 and ITC’99 b15 benchmark circuits. The experimental results show that, in comparison with the existing architectures, the Bpath-RO delay measurement scheme improves the circuit performance by an average of 13.81% (s298) and 3.47% (b15) and reduces the hardware overhead by up to 70% for each path.

In the era of information explosion, the issues of information security are of broad concern. The physical unclonable function（PUF） and the true random number generator become the basic security primitives, providing a lightweight solution. An entropy source separation model is proposed in this paper, which can separate the delays caused by jitter（the entropy of the true random number generator） and process deviation（PUF entropy） in a ring oscillator. A reconfigurable dual-mode circuit on FPGA was designed, which could reconfigure the PUF circuit into a true random number generator circuit by changing the mode. The proposed structure has the advantages of small resource overhead, large area utilization and low power consumption. The experimental results show that the PUF generated by the proposed structure has excellent performance in stability, uniqueness, and uniformity. The true random numbers generated by the proposed structure have high randomness and unpredictability. In addition, all true random numbers have passed the NIST test.