A method is described for localizing damaged areas on IC chip using ionization response maps. The method can provide some essential information to IC designers to help them improve its resistance to failures.

В аналитическом обзоре рассмотрены особенности радиационного поведения современных субмикронных микроэлектронных приборов при снижении проектных норм, а также перспективы развития обеспечивающей инфраструктуры для радиационных испытаний.

An advanced thermoelectric system has been developed to set a low temperature to the heat-generating power semiconductor devices. The system provides the setting the temperature down to -60°C in a volume of 80x40x12 mm3 at the heat-release up to 13 W. Accuracy of setting the temperature is in the range of ± 3°C. The design of developed system is adopted for long-term tests, including tests in harsh environment. The cooling chamber in may be placed up to 6 m away from the heat exchanger and control unit. One of the main features of new development is its mobility and easy installation when carrying out various types of tests.

A description of the system for setting a lowered environment temperature based on Peltier modules is presented. The development was carried out taking into account the peculiarities of the radiation test: minimum distance from exposure source to DUT; stand-alone use during long-term radiation test; minimum overall dimensions, transportability and flexibility when conducting tests on various exposure sources. Cooling box consists of 3-level stacked assembly of the Peltier modules, which is cooled by liquid refrigerant. Control of the assembly of Peltier modules was performed according to proportional integral and differential algorithm, provided by microcontroller with feedbacks on Pt thermoresistors. The system provides temperature stabilization of the DUT up to 23х17х12 mm in size and with released heat power up to 0.4 W at minus (60 ± 3) ºС. Temperature establishing time is less than 10 minutes. Typical power consumption of developed system is about 500W.

We provide a brief evolution trends overview of the modern microelectronic devices and its radiation behaviour, focusing on new structures and materials effects due to Total Ionizing Dose (TID) and Single Event effects (SEE) in CMOS elements. Evolution of test facilities driven by these changes in radiation behaviour of modern devices is also considered.

Экспериментально определена область безопасной работы высоковольтных диодов Шоттки на структурах 4H-SiC иностранного производства. Исследована деградация 4H-SiC изделий при воздействии накопленной дозы ионизирующего излучения. Проведено сравнение с аналогичными данными для высоковольтных приборов кремния. The paper highlights safe operating area for several types of high-voltage 4H-SiC Schottky diodes. Degradation of electrical parameters has been studied experimentally for several types of 4H-SiC power devices. Comparison with Si power devices has been carried out.

Heavy-ion-induced single event burnout (SEB) is studied experimentally for several types of 4H-SiC Schottky power diodes with various bias voltages applied. Safe operating voltage area for each type was defined and analyzed. The comparison with Si power devices was carried out.

The SEB test results of 3 kinds and 17 types of power MOSFET were systemized in this work. Several common features of radiation behavior were found for tested devices. The approach to increase SEB sustainability area of MOSFET-based electronic devices was discussed.

A methodical approach for the identification of a plant and characterization of integrated circuit technology based on an analysis of the features of a radiation response is proposed.

Several approaches to nondestructive procedure of total ionizing dose hardness prediction and grading of each sample within a wafer or a packaged lot of SOI (silicon-on-insulator) and SOS (silicon-on-sapphire) CMOS ICs are presented. Proposed approaches may be used as an operation of SOI/SOS ICs manufacturing process.

The optimal laser wavelengths for transient ionizing response due to dose rate effect simulation of 0.24 um CMOS SOI devices was found to be 0.56 um for top side irradiation and 1.06 μm for backside irradiation.

This work presents a solution for radiation hardness grading procedure using compact X-ray facility built in probe station, with automated measurement system based on NI PXI platform. The radiation grading procedure can be integrated as additional stage to provide rad-hard option of conventional process. Using the radiation grading procedure as a stage of IC fabrication process, the total ionizing dose (TID) hardness capability was estimated for commercial 65-nm CMOS test structures.

The approach developed in this work allows one to estimate limiting characteristics of single or series of impacts to provide guaranteed further functionality of modern ICs. It may be used also to estimate fault probability after one or series of impacts with known characteristics.

The work is devoted to the research of the single and multiple latch-up impact on the subsequent behavior of electrical parameters and operability of modern integrated circuits. The impact of interrupted SEL amount on subsequent behavior of IC is introduced. An approach to the estimation of the maximum time in the latch-up state is formulated to ensure IC’s fault-free operation after SEL.

The article is devoted to an automated system for parameters monitoring of the input and output chains of the logic ICs in order to identify its manufacturer. The system based on National Instruments PXI platform. The hardware and software parts of the system, as well as the measurement process and results threat, are observed.

This work presents a solution for radiation hardness assessment using compact and productive X-ray facilities, as well as,the automated measurement system. The radiation test procedure can be integrated in commercial IC's process as a mandatory option for providing high reliability and radiation hardened IC projects. Using the radiation test procedure as a one of technology stage, the assessment of total ionizing dose (TID) hardness was done for test structures, which were fabricated in conventional 65 nm CMOS technology. (C) 2016 Published by Elsevier Ltd.

The effect of the direction of laser polarization on the transient radiation response of an IC memory device implemented using CMOS technology 0.18 μm is estimated. The effect of laser polarization is investigated both for local exposure and exposure on the entire crystal. It is shown that the direction of laser polarization should be taken into account when simulating local dose rate effects.

Pulsed laser sources are widely used for high dose rate effects modeling in modern ICs. In this research, a significant effect of optical beam polarization orientation on ionization response of ICs with design rules of less than the laser wavelength was demonstrated. This approach suggests taking into account the influence of a laser parameters on IC's dose rate response.