This paper introduces a novel tunable oscillator-based impulse radio ultra-wideband transmitter, implemented in 28 nm HPC TSMC CMOS technology. The transmitter employs a differential ring voltage-controlled oscillator to achieve wide tuning across low and high-frequency bands, ensuring compliance with FCC, ECC, Japan's spectrum masks, and IEEE 802.15.6 standard. Operating at a data rate of 40 Mbps, it features low power consumption below 1 mW and an ultra-compact design footprint of just 0.0019 mm 2 , making it ideal for neural recording implants. The transmitter achieves energy efficiencies of 2.75% and 1.52% in the lower and upper bands, respectively, with output power of approximately -15 dBm and -17.8 dBm. Additionally, it attains a Figure-of-Merit of 17.4 and 9.5 (1/ mm 2 ) in the upper and lower bands, respectively, highlighting its superior area and power efficiency.
The Multiple-Value Logic (MVL) circuit significantly enhances propagation delay and energy consumption compared to the binary circuit. Additionally, the Carbon Nanotube Field-Effect Transistor (CNTFET) demonstrates enhancements in energy efficiency and circuit speed when compared to other transistor technologies. Therefore, this paper proposes two different designs of Ternary Decoders (TDecoders) using CNTFET, which can create additional ternary circuits such as ternary adders, multipliers, and multiplexers. The investigation and proposed TDecoders were simulated and tested with the HSpice simulator. The simulation results demonstrate the approach's merits in reducing energy consumption by over 65% and 10% compared to the standard design and the best-case design, respectively.
This paper presents a novel MEMS and ASIC-based sensor system for simultaneous detection of magnetic fields and patient movement. The prototype system integrates a three-channel current-reuse amplifier and three MEMS cantilevers on independent PCBs. The amplifier, fabricated in 350 nm CMOS technology, exhibits a closed-loop gain of 10 V/V, a low power consumption, and a noise floor of 18 nV/root Hz. In combination with three MEMS cantilevers (3 mm x 1 mm) in a 3D-configuration this setup is able to detect vibrations and movement. The cross-axis sensitivity of this setup was measured as 20% for one directional vibration on a shaker. The system successfully detected the 3D-acceleration of human footsteps.
The quality of training data is a critical determinant of the performance, reliability, and predictive accuracy of any AI model. Federated learning provides a promising framework for developing global AI models in distributed computing environments, where individual data nodes can maintain data privacy while contributing to a shared model. Although each node can locally enhance the quality of its data, the distributed nature of the system does not guarantee global data quality. One of the main challenges arises from heterogeneity introduced by federated learning is data quality, which often result in global data degradation. Despite the increasing focus on the challenge of Non Independently and Identically Distributed (NIID) datasets, data quality is often regarded as a subset of this problem and not fully explored in its own right. In this paper, we introduce a comprehensive node scoring approach designed to enhance quality awareness without relaying on a shared reference dataset. The scoring approach focuses on assessing global data quality with respect to variations in data volume, label imbalance, global duplicates, and label preference skew. The proposed Quality scoring is utilized to either determine nodes respective weights in Fedq aggregation method. It is used also in sorting and sampling nodes for further selections. To evaluate the proposed node scoring method, the paper introduces a simulation model based on the MNIST dataset. The introduced model simulates extreme low level of data quality nature of the federated data and uses this data to evaluate the proposed scoring approach versus the baseline FedAvg and Irrelevance score in terms of global model accuracy, model stability and model convergence with particular attention to the content diversity score, which quantifies global duplicity.
This abstract provides an overview of an article focusing on the integration of the Internet of Vehicles (IoV) with electric vehicle (EV) charging infrastructure to enhance transportation sustainability and efficiency. It emphasizes the importance of efficient EV charging planning in identifying suitable charging stations while addressing constraints such as State-of-Charge (SOC) and driving direction. The proposed IoV-based scheduling scheme aims to minimize travel distance and charging costs, meet EV charging time requirements, and optimize charging station resource utilization. The study employs artificial neural networks to determine the optimal charging moment, with simulations conducted using Matlab-Simulink and a DSP board for trained data. Morocco is selected as the study area for this research.
This paper presents a highly sensitive Hall sensor with a high-performance instrument amplifier interface circuit fabricated in a 0.18 mu m CMOS process. The Hall sensor is optimized with an equivalent model that achieves a high sensitivity of approximately 25.82 mV/VT under a magnetic field intensity of 60 mT. The instrument amplifier employs a capacitance-coupled instrument amplifier (CCIA), consisting of a chopper for noise reduction, a positive feedback loop for input impedance boosting, and a ripple reduction loop to suppress chopping ripple. Experimental results demonstrate that the CCIA achieves a gain error of less than 0.1% with a noise floor of 223 mu V/root Hz @ 4 Hz. The integrated testing system is suitable for tactile sensing, biological applications, and micro compasses.
In this paper, we design and simulate a partial ground plane (PGP) based junctionless transistor (JLT) that overcomes the inefficient volume depletion of charge carriers associated with silicon on insulator (SOI) based junctionless transistor in the OFF-state. A single high workfunction gate-metal is not sufficient enough to obtain volume depletion due to the carriers flowing at the bottom of the channel region, resulting in substantial subthreshold leakage. The combination of PGP and the SELBOX features in the proposed device achieves better volume depletion in the channel region, thereby reducing the OFF-state leakage current and improving the ION/IOFF ratio significantly. Further, the self-heating issues of the SOI based junctionless transistor has got resolved by invoking the concept of SELBOX. The opening in the oxide has provided a path for the heat generated inside to get efficient dissipated. Calibrated simulations have revealed that the proposed PGP based junctionless SELBOX transistor outperforms the conventional SOI junction less transistor substantially, in term of ION, ION ratio, short channel effect suppression, leakage etc. Further, it has been observed that the performance can be further optimized by optimizing the substrate and the PGP doping concentrations in the proposed device.
Skin cancer is a highly prevalent form of cancer worldwide. The clinical assessment of skin lesions is crucial for evaluating the disease's characteristics. However, this assessment is often hindered by the variability in interpretations and lengthy timelines, resulting in delayed diagnoses. An advanced computer-aided diagnosis (CAD) system is needed to improve patient survival rates. This paper presents a Multi-class Skin Cancer Classification system using an enhanced VGG-16 model to improve the diagnosis of skin cancer. Our approach focuses on classifying multiple skin lesions types, specifically Melanocytic Nevus $(NV)$ , Basal Cell Carcinoma $(BCC)$ , Melanoma $(MEL)$ , and Vascular Lesions $(VASC)$ . The system was trained and evaluated on the Human Against Machine with 10,000 training images (HAM10000) dataset. We have conducted a comparative study between our method and several previously introduced techniques on the International Skin Image Collaboration (ISIC) dataset, and the results show that the proposed model outperforms previously proposed techniques.
Each generation of the wireless communication networks has contiguous demands for higher computing capabilities and lower the power consumption in the integrated circuitry. Thus, the optimization of the base-band signal processing kernels and the hardware architectures plays a pivotal role in the performance, latency, and energy efficiency of the Physical Layer (PHY). Channel Estimation (CE), a computationally intensive task with hard real-time requirements, involves significant amounts of matrix multiplications and inversions, when data flows between transmitter (TX) and receiver (RX). In this work, we present a software implementation of CE for the 5th Generation Cellular Networks (5G) New Radio (NR) in the Reduced Instruction Set Computer (RISC)-V architecture, showcasing how its vector processing capabilities can satisfy the throughput and delay requirements of 5G use cases. Specifically, we ported two CE kernels, the Least-Squares (LSE) and Minimum Mean Square Error (MMSE), onto a state-of-the-art single core vector processor. By exploiting data vectorization, the ARA core computes matrix arithmetic operations on multiple data sets simultaneously. Our single vector core serial optimization demonstrates that with a 16x16 matrix window size and 16 vector lanes, the application's performance achieves a speedup of 78.27 when computing the LSE algorithm. When the number of operations per cycle are compared, the vector processor outperforms its scalar counterpart by 181.91 for the MMSE kernel. Our implementation orders the nested loops in a latency-reducing fashion to compute matrix arithmetic operations, resulting in LSE and MMSE estimator computing times of 8.44 mu s and 12.31 mu s, respectively.
Business Process Modeling plays a critical role in improving operational efficiency, consistency, and transparency within organizations. Despite the significant focus on syntactic and semantic aspects, pragmatic quality, the clarity and comprehensibility of BP models, remains underexplored. This paper addresses this gap by proposing a Large Language Models approach to enhance the naming of XOR split outgoing edges in BPMN models. The proposed method automates the generation of clear, meaningful, and contextually appropriate edge labels. These labels are evaluated using the all-MiniLM-L6-v2 model, a pre-trained sentence transformer that maps sentences into a dense vector space, enabling semantic search and clustering. Our results show that this LLM-based approach significantly improves the pragmatic quality of BPMN models, enhancing both model clarity and decision-making efficiency.
This paper proposed the design and implementation of a high-data-rate neural interface system capable of transmitting data from 128 neural electrodes at the sampling rate of 32 KS/s, achieving a data rate of up to 96 Mbps. The transmitter utilizes 16-QAM modulation and operates within the 420-450 MHz frequency band with a power consumption of 5.8 mW. The receiver specifically adapted for the real-time operation corresponding to the transmitter was designed by FPGA and ADRV9009.
Energy optimization is critical in smart home systems and IoT networks, necessitating innovative models that reduce energy use. This research presents two Long Short-Term Memory (LSTM) network models for estimating home power consumption using time-series data. The first model employs a standard LSTM technique with multivariate characteristics including global active power, voltage, and sub-metering variables. This technique strikes a balance between prediction accuracy and computing economy, making it ideal for resource-constrained applications. The second model provides an optimized version of the LSTM, which uses PyTorch and Ray Tune for hyperparameter optimization. The optimization focuses on tweaking learning rates, batch sizes, and LSTM layers to improve model accuracy and convergence speed. Using hyperparameter tuning, the Mean Squared Error (MSE) for global active power forecasts is decreased to 0.0018, proving its appropriateness for low-resource IoT systems. Both models are tested on a resampled real-world household electric power consumption dataset for effective training. The study emphasizes the advantages of multivariate time-series analysis and hyperparameter optimization, demonstrating that the optimized LSTM model can accurately predict energy consumption, enhance energy management in smart homes, and lower computing costs. Future work will look into combining more IoT data streams and real-world deployment for further improvement. The findings add to the expanding body of knowledge about energy optimization in IoT environments, addressing the crucial demand for effective, real-time energy management systems.
This paper develops and assesses multiple optimized Machine Learning (ML) based techniques to discover the appropriateness of them in modelling small-signal behaviors of Gallium Nitride High Electron Mobility Transistors (GaN HEMTs). At first, ML techniques namely Gaussian Process Regression (GPR), Generalized Regression Neural Networks (GRNNs), Radial Basis Neural Networks (RBNNs), and Artificial Neural Networks (ANNs) based behavioral models for GaN HEMTs are developed. Then, the developed models' accuracy and efficiency are further enhanced using rigorous hyperparameters optimization. At last, the optimized models are compared using conventional metrics namely mean squared error, mean absolute error, coefficient of regression (R2), time required to train the models, and the ability to imitate the behavior at biasing conditions. We found GPR-, GRNNs-, RBNNs- and ANN-based models provided average %R-2 = 99.77, 99.44, 99.22 and 99.86, and required training time = 337.8 (s), 21.04 (s), 683.47 (s) and 17.8 (s), respectively.
We experimentally demonstrate wavelength-selective metasurfaces operating in the mid-infrared spectral range extending from 1000 to 25000 nm. Resonant peaks are observed in the 13000-17000 nm range. The metasurface consists of micrometer-scale one dimensional periodic gratings made of highly-doped silicon using conventional ultra-violet lithography, taking advantage of its plasmonic behavior in the infrared. Simulations results supports understanding the effects of key parameters including the doping concentration and the gratings period.
Fractional- $N$ frequency synthesizers are notorious for producing spurious tones (spurs) whose frequencies depend explicitly on the fractional part of the frequency control word. It is often assumed that the worst-case fractional spur is the so-called integer boundary spur (IBS). The Periodic Nonlinearity Noise (PNN) concept has been used to predict the absence of nonlinearity-induced spurs. This paper shows how the PNN can also provide insight into the production of fractional spurs. It shows (i) that the spur pattern is independent of the fractional part of the control word when the latter is small, (ii) that the IBS is not always the worst case, and (iii) why a second-order IBS or fractional boundary spur (FBS) might be higher than the IBS. Simulations and insights are correlated with experimental observations.
Optimizing Convolutional Neural Networks (CNNs) for hardware deployment has gained significant attention as the number of edge devices continues to grow. This is driven by the realization that edge computation reduces bandwidth usage and, consequently, overall power consumption. The first CNN layer, in particular, is receiving increased focus due to its direct impact on the network's overall accuracy. This paper provides an overview and summary of various first-layer optimization techniques. Additionally, a Hardware-Aware Technique (HAT) is proposed and evaluated for its potential as a first-layer optimization method. A comparison between the proposed HAT and other leading techniques, based on overall network accuracy and the quality of first-layer feature maps, demonstrates that the HAT is a strong candidate for first-layer CNN optimization. In a custom CNN architecture using a dataset acquired by a CMOS image sensor (CIS), the proposed HAT achieves a validation accuracy of 96.49%, which is highly competitive with other state-of-the-art approaches.
Efficient industrial manual assembly lines provide high-quality products. Reliable portable assistive tools help workers finish manufacturing tasks efficiently. The Microchip AVR family of 8-bit microcontrollers is widely used in electronic products, which includes the AT, ATtiny, ATmega, and ATxmega subfamilies. This paper proposes a design of a reliable rechargeable Microchip AVR In-Circuit Serial Programmer for programming Microchip AVR AT, ATtiny, and ATmega microcontrollers deploying the Programmer-To-Go functionality. It uniquely features a rechargeable Lithium-Ion battery, automatic selection of programming speed up to 4MHz, 3V-5V programming support, a microSD card that stores the firmware files required for programming, and an attached monochrome LCD that enables reliable ad-hoc programming. It supports Flash and EEPROM memories, Fuses, and Lock Bits reading, writing, verifying, and erasing based on the Microchip AVR STK500 communication protocol. Experimental work was conducted on the Arduino UNO development board. The results proved efficient programming (writing) time of 3s and 5s for 5KB and 20KB .hex files, and reading time of 5s and 7s of the same .hex files.
In this study, a pure analog integrated ReLu-based artificial neural network architecture is presented. This encompasses circuits operating in the sub-threshold region, such as the sigmoid function circuit, analog cascode current mirrors, an operational amplifier-based voltage comparator and on-off Rectified Linear Unit circuit. This architecture is tested on a water quality classification problem. The overall implementation consumes 310nW and achieves an average accuracy of 83.81%. The architecture is designed and verified in a TSMC 90nm CMOS process. Additionally, post-layout results are compared both with software implementations and with existing literature.
Recently Bidirectional Encoder Representations from Transformers (BERT) model has gained lots of attention because of its state-of-the-art performance in multiple natu-ral language processing (NLP) tasks. However, just like many other deep learning based tasks, large model size and intensive computation load of BERT make it difficult and expensive to run and implement on general purpose processors. The proposed hardware accelerator for BERT model realizes faster inference speed and higher energy efficiency. Design procedure is elaborated with two stages: model compression and hardware architecture. Quantization is chosen as the compression technique because of good speed-up performance as well as small model size and less complexity. In the hardware design, systolic tensor array (STA) is applied as processing elements (PE) array to achieve lower area and power consumption by reducing the ratio between registers and number of Floating-point operations per second (FLOPS). Dedicated hardware is designed for Softmax and layer normalization operations. Mathematical transformation is used to replace complicate nonlinear functions with simple operations to reduce the required hardware resources. Performance is evaluated based on transformer-base model. The maximum speed of overall hardware design is 125 MHz and the total latency is 165.9 us. Compared to the same task run on GPU, 22.4x and 7.5x speed up are achieved in multi-head-attention (MHA) and feed-forward networks(FFN) separately. The peak performance of this design is 4.1 TOPs/s and the maximum required memory bandwidth is 80 GB/s.
In the context of Industry 4.0, It is undeniable to have an optimized system capable to detect equipment failure. For this purpose, Machine Learning models are used as a decision making approaches to this problematic. Furthermore, we generated a synthetic dataset to validate the approaches. This dataset represents real world of industrial applications and gives data for prior estimation of a failure of a machine based on several variables such as temperature, torque, rotational speed, and tool wear. We trained and compared six machine learning models a Random Forest, XGBoost, SVC, K-Nearest Neighbors, Logistic Regression, and Multi-Layer Perceptron on their performance in predicting machine failures. The study shows that Random Forest was the most accurate model that recorded an overall accuracy of 99% making it suitable to be used in predictive maintenance within the IIoT environment. Finally, this research demonstrates how synthetic data enhances predictive maintenance solutions.
