In addition to the conventional ADC design tradeoffs between power, speed, and accuracy, radiation tolerance is the fourth factor for ADCs used in radiation environments. This paper describes radiation-tolerant (RT) ADC design tradeoffs and design strategies. Then, the paper introduces a 13-bit RT pipelined-successive-approximation register (pipelined-SAR) ADC fabricated in 65 nm CMOS technology based on the concluded tradeoffs. To further improve the ADC power efficiency, a semi-time-interleaved (Semi-TI) structure is employed. Besides, the ping-pong auto-zeroing (AZ) scheme is implemented in the residue amplifier (RA) to reduce the TID-induced offset while maintaining low power dissipation. The proposed ADC is designed and hardened against Single Event Effects (SEEs) and Total Ionizing Dose (TID) effects from the structure to layout levels. All sub-blocks were examined, and only the critical blocks were hardened to avoid over-hardening. From the measurement results, the prototype ADC attains an 80 MS/s sampling rate and achieves 70.8-dB SNDR and 80.3-dB SFDR at the Nyquist input frequency. With a total power consumption of 13.8 mW, the prototype ADC establishes a state-of-the-art Walden Figure of Merit of 60.7 fJ/conv step, yielding an efficiency comparable to non-RT ADCs with similar specifications. Irradiation tests validate the consistent performance of the ADC up to a cumulative dose of 500 krad (Si) in X-ray testing, while laser testing indicates a robust SEE threshold and swift post-SEE recovery.

In modern medical, aerospace, and high-energy physics applications, radiation tolerance in ADCs is crucial to guarantee the signal chain's robustness. However, it usually brings penalties to the power efficiency. Double modular redundancy and averaging are used in [1] to detect and ignore the error samples caused by radiation effects. [2] applies a higher power supply to minimize the radiation-induced degradation. However, the previous works did not consider the ADC efficiency degradation caused by radiation tolerance. This paper presents a pipelined-SAR ADC, which is designed by revealing and balancing the tradeoffs between power efficiency and radiation tolerance, achieving 80MS/s and 70.79-dB SNDR with high conversion efficiency and radiation tolerance.

We present the total ionizing dose (TID) dependencies of output resistance of the 1.8 V and 1.5 V Stub Series-Terminated Logic (SSTL18/15) transmitter drivers fabricated with a commercial 65 nm technology. The analysis showed the radiation-induced resistance growth that was attributed to the interface trap build-up in unsalicided polysilicon resistors. The growth accelerates at a low dose rate. We also discuss the results for 24 hours of annealing at room temperature followed by high-temperature annealing for 168 hours, the layout dependencies, and the significance of the observed effects at higher absorbed doses.

Ahstract- We propose a layout-aware fault injection technique for Single Event tolerant integrated circuits design. Being fully compatible with standard verification flow, the proposed technique is applied to AES crypto cores implemented with TMR.

We propose a total ionizing dose tolerance estimation of a previously presented all-MOS voltage divider that can be used in space-bourne and high-energy physics equipment working in harsh environment. The proposed circuit works well in both MOSFET weak and strong inversion modes. The estimations are made by means of SPICE simulation with threshold voltage changes according to available theoretical and experimental data.

The development of trusted fault-tolerant VLSI requires achieving economic efficiency, along with the functional and operational characteristics for the target equipment. To minimize errors, reduce costs and time to market, the practice of “reusing” technical solutions in the form of complex functional blocks (IP blocks), element libraries, etc. is widely used. In case the developers are not limited by various kinds of sanctions, they can choose the basic technical process for their project among several options according to the same design standards. The choice of a non-optimal for a given product and less stable technical process with a low-quality set of design tools leads to non-fulfillment of the requirements for the developed components or to the uncompetitiveness of the developed IP. Since it is almost impossible to localize the production of all the necessary electronic components, it is reasonable to determine the main technological directions for localization, while for all used processes to achieve the highest possible level of reuse of IP and libraries, ensuring the highest possible yield and a large series, apply a platform approach. The study considers multifactorial aspects of the design and development of platforms dedicated to trusted fault-tolerant systems on the levels of electronic component base (systems on a chip) and radio-electronic equipment (systems in package, micromodules and the corresponding infrastructure of support and services). We propose the solutions based on standard assembly components and allowing to implement the required functionality, increase economic efficiency and provide the high level of reliability and security, including the circumstances of sanctions restrictions.

As already announced, we are opening a new regular column "There is an opinion", and as a first experience, we invited Maxim Gorbunov, Ph.D., Associate professor of the MEPhI National Research Institute, who, in collaboration with Ph.D. Danilov Igor, will express an opinion on the topic "What could be the program for creating domestic CAD systems?". This is the author's view based on the experience of developing complex functional blocks using current domestic and foreign CMOS technologies, as well as software tools for modeling radiation effects in the standard design route. In addition, M.S. Gorbunov took an active part in the preparation of programs and subprograms for the creation of domestic CAD systems, which, unfortunately, for various reasons did not start. Given the relevance of this problem for the development of a wide range of domestic ECB, including trusted, we believe that the view on the organization of such work is at least interesting.

We propose a MOS temperature-insensitive voltage divider circuit. The circuit works well in both weak inversion and strong inversion modes. The temperature insensitivity of this device is derived analytically and demonstrated by simulation. We also propose a voltage reference circuit based on the divider. We use a 90 nm CMOS Process DesignKit (PDK) to provide SPICE simulation.

We study the total ionizing dose (TID) effects sensitivity of 180 nm Silicon-on-Insulator (SOI) microwave low-noise amplifier (LNA) parameters. We use the previously developed Verilog-A based model to explain the results obtained.

We present a study on the layout design of the rad-hard standard logical cells and fault-tolerant static random access memory (SRAM) cells. We used the previously developed layout-aware SPICE-based simulation technique to check the design patterns that involve sensitive node spacing and contact placement to increase the tolerance to multiple node upsets. The results of the simulations were transformed into layout design recommendations verified by the simulation and experimental data for SRAM cells with layout design supporting the recommendations. The results proved the efficiency of the proposed hardening measures.

В аналитическом обзоре рассмотрены особенности радиационного поведения современных субмикронных микроэлектронных приборов при снижении проектных норм, а также перспективы развития обеспечивающей инфраструктуры для радиационных испытаний.

We provide a brief evolution trends overview of the modern microelectronic devices and its radiation behaviour, focusing on new structures and materials effects due to Total Ionizing Dose (TID) and Single Event effects (SEE) in CMOS elements. Evolution of test facilities driven by these changes in radiation behaviour of modern devices is also considered.

Представлены отечественные разработки, позволяющие моделировать радиационные эффекты космического пространства в рамках стандартного маршрута проектирования СБИС.

We present a comparative analysis of the layout-aware fault injection simulation results for Direct Memory Access (DMA) controllers with local, distributed, global and block Triple Modular Redundancy TMR). The applied technique is also presented.

We discuss the main design concepts for fault-tolerant microprocessors, Instruction Set Architectures (ISA) of microprocessors for space applications and the achievable characteristics considering the KOMDIV microprocessors designed by SRISA. The trade-off between the fault-tolerance, performance and power consumption is considered for microprocessors designed using the silicon-on-insulator (SOI) and bulk CMOS technologies.

We showed that the Hsiao decoder circuit could be minimized, resulting in the delay or area reduction without significant increase of the decoder failure ratio. We designed three versions of the decoder (full, shortened and minimized) and showed that it is possible to reduce its delay time by 13-18%, or the area by 33-57% relative to the full version. Also, we showed using fault injection simulation that the value of the failure ratio varies from -8% to +6% for shortened and minimized versions relative to the full version.

Compact modeling of inter-device radiation-induced leakage underneath the gateless thick STI oxide is presented and validated taking into account CMOS technology and hardness parameters, dose-rate and annealing effects, and dependence on electric modes under irradiation. It was shown that proposed approach can be applied for description of dose dependent static leakage currents in complex FPGA circuits.

We present the direct experimental vulnerability comparison of two microprocessor designs with different Single Event Effects (SEE) mitigation techniques at different heavy ion fluxes. The trade-off between the performance, fault-tolerance and power consumption is considered. We introduce the Mean Fluence Between Failures (MFBF) metric for the vulnerability comparison.

Space radiation interacting with electronic components of on-board computing or navigation unit can bring to it's malfunction. Using error tolerant electronic components is a key factor ensuring safety of Space missions. The Muller C-element is one of the main part of the asynchronous circuits and also can be found in synchronous ones. Being sequential by its nature, it is vulnerable to single event upsets. We propose three CMOS circuit implementations of a soft error tolerant Muller C-element, whose tolerance is achieved by using of the well-known DICE-principle and is proved by SPICE simulations.