In response to the growing demand for advanced memory technologies, this study investigates a 4 Mb phase-change memory (PCRAM) chip employing a carbon-doped Ge2Sb2Te5 (C-GST) dielectric material to achieve multistage storage. The Partial-RESET programming and verification (P&V) method was utilized to effectively create intermediate-resistance states, facilitating multilevel storage. The study focuses on optimizing the key parameters affecting the P&V method to enhance the precision and efficiency of reaching intermediate resistance values. Through comprehensive experimentation on the PCRAM array, this work evaluates the performance of multilevel storage, providing insights into the potential for scalable, high-density memory applications.

Interface-influenced crystallization is crucial to understanding the nucleation- and growth-dominated crystallization mechanisms in phase-change materials (PCMs), but little is known. Here, we find that composition vacancy can reduce the interface energy by decreasing the coordinate number (CN) at the interface. Compared to growth-dominated GeTe, nucleation-dominated Ge2Sb2Te5 (GST) exhibits composition vacancies in the (111) interface to saturate or stabilize the Te-terminated plane. Together, the experimental and computational results provide evidence that GST prefers (111) with reduced CN. Furthermore, the (8 - n) bonding rule, rather than CN6, in the nuclei of both GeTe and GST results in lower interface energy, allowing crystallization to be observed at the simulation time in general PCMs. In comparison to GeTe, the reduced CN in the GST nuclei further decreases the interface energy, promoting faster nucleation. Our findings provide an approach to designing ultrafast phase-change memory through vacancy-stabilized interfaces.

In this paper, GaGST films with different Ga contents were prepared by co-sputtering of Ge3.4Sb2.3Te5 target and Ga2Ge3.8Sb2.3Te5 target to obtain a high-speed and low-power phase change material. The present data emphasize that compared with Ge2Sb2Te5, Ga0.4Ge3.5Sb2.3Te5 exhibits a higher crystallization temperature(193 degrees C) and better data retention ability (108 degrees C for 10 years). XPS results show that Ga and Sb combine to form GaSb, and it reduces the density change after crystallization of GaGST material to 2.7%. At the same time, it has a smaller grain size(similar to 5-10 nm) and a lower drift(< 0.059). Furthermore, the behavior of reversible phase change can be realized by a 6 ns width electric pulse, and the power consumption under the action of this pulse only needs an ultra-low power consumption of 0.16pJ. The results of materials and devices show that Ga0.4Ge3.5Sb2.3Te5 is a very suitable material for phase-change memory(PCM).

For improving the three-dimensional structure of phase-change memory devices, Ovonic threshold switch devices have received renewed attention as selectors owing to a simple production process, good scalability, and excellent performance. It can replace transistors and diodes in the available technology. In this article, we studied the GeSe-based chemical mechanical polishing process. The different concentrations of hydrogen peroxide and lysine interacting with GeSe in chemical mechanical polishing were investigated. Material characterization was performed by scanning electron microscopy and atomic force microscopy. In addition, the reaction mechanism in the chemical mechanical polishing process was analyzed by electrochemical experiments and X-ray photoelectron spectroscopy.

The heating electrode contact (HEC), as the key part for collecting current and transferring heat in phase change memory (PCM), tends to be unevenly oxidized by the external SiO2 coating layer during manufacturing and fatigue, resulting in negative effects on the performance of PCM. In this paper, WN film is used as the protective layer to avoid oxidation of TiN HEC. The RESET/SET current of PCM cells is reduced because of the oxygen barrier and heat preservation effect of WN film. In the endurance test of HEC, the cycle times of TiN electrode double-coated by WN can reach 1012, which is significantly higher than the electrode double-coated by SiO2. Besides, the endurance characteristics of PCM cells with this new structure of HEC are proved to be better.

The blade bottom electrode contact (BEC) can significantly reduce the programming current of the phase change memory (PCM) and achieve low power consumption compared with the typical T-shaped PCM cell. The method of controlling the electrode width by controlling the thickness of the deposited layer can make the size break through the limit of photolithography. This paper proves that the RESET programming current and power consumption of the PCM decrease linearly with the decrease of the blade BEC width, and builds a theoretical model to verify it by simulating the distribution internal temperature field. Based on the above research, the cell life of PCM with different electrode widths was tested, and it was proved that the endurance of PCM increased with the decrease of the width of the blade electrode, caused by the lower power consumption of the narrower electrode.

128 Mb Phase Change Memory (PCM) chips show potential for many applications in artificial intelligence. A PCM cell often has a sandwich structure that consists of a TiN bottom electrode, a phase change material, and a top metal. TiN films prepared by atomic layer deposition have high thermal stability, and a WN coating layer on the TiN electrode can prevent oxidation in the electric and thermal field, achieving high endurance of the TiN electrode over 1011 cycles. In the phase change material of carbon-doped Ge2Te2Te5 (CGST), C-C chains and C clusters precipitate at the Ge2Te2Te5 (GST) grain boundaries, which effectively refines the grain size of GST. The C confinement enhances the Ge/Sb atomic migration barrier and suppresses the composition segregation in the Reset/Set operation process and the atomic relaxation of the CGST material. As a result, the endurance and conductivity-drift of the PCM chip were enhanced. Finally, stability over 5 × 108 cycles and 12 multi-level stable states were achieved in the 128 Mb PCM chip. This work presents a step towards the realization of large-scale and energy-efficient neuromorphic computing systems.

Titanium nitride (TiN) is preferred for use as the bottom electrode contact due to its excellent thermal stability and suitable electrical conductivity. We have studied the effect of using potassium permanganate (KMnO4), L-Aspartic Acid (L-Asp) and alumina abrasives as slurry in chemical mechanical polishing (CMP) of TiN film. Different concentrations of potassium permanganate and different concentrations of L-aspartic acid additives were applied to the CMP of TiN. The results show that KMnO4 and L-Asp can increase removal rate and improve the surface smoothness of TiN. The removal mechanism of TiN was analyzed by XPS and electrochemical tests, and the TiN film was characterized by atomic force microscope and scanning electron microscope.

Correction for ‘12-state multi-level cell storage implemented in a 128 Mb phase change memory chip’ by Zhitang Song et al., Nanoscale, 2021, DOI: 10.1039/d1nr00100k.

Many experiments have shown that three-dimensional-confined grain refinement (GR) textures in phase-change memory reduce power consumption and improve endurance performance. However, a lack of knowledge on the GR mechanisms and their influence on device performances challenges designs that concurrently enhance the comprehensive device performances using the same impurity-doped strategy. Here, we experimentally observe dramatic GR in carbon-doped Ge2Sb2Te5 (GST), which also presents reduced power consumption and enhanced endurance performances. We provide low power consumption evidence that thermal conductivity controls the thermal transport heat loss and is proportional to the size of nanoscale grains because the boundary severely scatters phonons. Our simulations indicate that the short carbon chains in the boundary interlace with each other and trend to form trialkyl carbon atoms that constitute the basic local environment of graphene. The stable sheet consists of aggregated carbon, which is even stable above the melting temperature of GST and acts as a second-phase drag to refine the grain size. The enhanced endurance is explained by the restricted migration from the stable carbon sheet, which is verified by the greatly reduced diffusion coefficient of the host atoms in the boundary because of the less shielding effect from the core electrons in carbon and strong bonds formed between host and carbon atoms. Our findings show that the reduced power consumption and enhanced endurance from GR engineering are feasible in phase-change memory, which has been largely overlooked.

In this paper, aiming at the consistency of driving current and the reliability of crosstalk current, we propose two methods to optimize the performance of the dual-trench epitaxial diode array for phase change memory (PCM), as well as the optimization calculation model. By inserting pickup and using the new bias scheme, we can improve the consistency of the diode arrays and reduce the impact of crosstalk current on the idle storage cell, respectively. The test results show that all the diodes in arrays, including 4F(2)in 40 nm process node, can provide a driving current of more than 900 mu A at 2.7 V, after inserting pickups. With the new bias scheme, the maximum of the crosstalk ratio in the 12F(2)diode array can be reduced to less than 2%, which is proved has no effect on the idle PCM cell. Moreover, the optimization model is the basis of design and fabrication to improve the performance of the diode access PCM chip.

Carbon (C)-doped Ge2Sb2Te5 material is a potential candidate in phase change random access memory (PCRAM) because of its superb thermal stability and ultrahigh cycle endurance. Unfortunately, the role and distribution evolution of C-dopant is still not fully understood, especially in practical industrial devices. In this report, with the aid of advanced spherical aberration corrected transmission electron microscopy, the mechanism of microstructure evolution manipulated by C-dopant is clearly defined. The grain-inner C atoms distinctly increase cationic migration energy barriers, which is the fundamental reason for promoting the thermal stability of metastable face-centered-cubic phase and postponing its transition to the hexagonal structure. By current pulses stimulation, the stochastic grain-outer C clusters tend to aggregate in the active area by breaking C-Ge bonding; thus, grain growth and elemental segregation are effectively suppressed to improve device reliability, for example, lower SET resistance, shorter SET time, and enlarged RESET/SET ratio. In short, the visual distribution variations of C-dopant can manipulate the performance of the PCRAM device, having much broader implications for optimizing its microstructure transition and understanding C-doped material system.

While phase-change materials (PCMs) composed of chalcogenide have different crystallization mechanisms (CM), such as nucleation-dominated Ge2Sb2Te5 (GST) and growth-dominated GeTe (GT), revealing the essential reason of CM as well as the tuned properties is still a long-standing issue. Here, we remarkably find the distinct stability of Te-terminated (111) boundaries (TTB) in different systems, which provides a path to understand the difference in CM. It stems from the quantum effect of molecular orbital theory: the optimal local chemical composition results in the formation of TTB without dangling bonds (DB) in GST but with DB in GT, where DB destabilizes boundary due to its distorted local environment mismatching Oh symmetry of p orbitals. Moreover, the inner vacancy concentration in GST is alterable and controlled by TTB, manifested by the absence of cubic-to-hexagonal transition in carbon-doped GST of small grains and minimized inner vacancy. Finally, the charge transport property (CTP) is controlled by boundary via changing the density of charge or hole nearby as well as vacancy. These findings open the door to tune CTP by CM, which is necessary for achieving low-power and ultrafast devices.

The invention relates to a biasing method of a memory device. A gate of the memory device is a diode array; the diode array comprises at least two bit lines and at least two word lines which are crossed; diodes are arranged at the intersections of the bit lines and the word lines; during normal gating operation, a gating signal is applied to the bit line BLn where the gating diode is located, a suppression signal changing along with the gating signal is applied to the bit line needing to eliminate the parasitic leakage current, other bit lines are grounded, a word line WLn where the gating diode unit is located is grounded, and voltages Vp larger than the gating signal and smaller than the reverse breakdown voltage of the diode are applied to other word lines. According to the invention, parasitic leakage current of adjacent bit lines can be reduced or thoroughly eliminated, and reverse leakage current of a small part of diodes can be reduced.

Phase change random access memory tend to provide the write speed close to that of DRAM to expand applications in stand-alone and embedded filed. The period of set operation is the key parameter to determine the write speed. In this paper, a method for optimizing each step width of a stair-case pulse is proposed. The width of each step can be adjusted according to the cell percentage for set current acquired from the lowest resistance point in the Resistance-Current curve. This method can solve the heating inconsistency problem of set operation and is beneficial to speed and set resistance distribution. The experiment results are gathered across a 16 Kb blocks of a 4 Mb PCRAM chip with 40 nm CMOS process. The resulting optimized stair-case set pulse speed is less than 100 ns. (C) 2020 The Electrochemical Society ("ECS"). Published on behalf of ECS by IOP Publishing Limited.

Endurance improvement is a crucial work for phase change memory (PCM) which has always been the focus of researchers, but fewer studies concentrate on parameter optimization to improve endurance. In this paper, the correlation between the RESET condition and the endurance of PCM has been investigated systematically based on sample cells of a 4 Mb embedded PCM chip through Statistical analysis. It is evidently clear from the test results that high and narrow RESET condition can bring a significant improvement in endurance. And a new test-time-saving method for optimizing RESET condition to improve endurance is proposed. Further, the power consumption and the temperature distribution of PCM during the RESET process has been studied. The results confirmed that high heating speed and less thermal damage to the operating electrode originated from the high-narrow RESET pulse all together account for the improvement of endurance. (C) 2020 The Electrochemical Society ("ECS"). Published on behalf of ECS by IOP Publishing Limited.

Phase change memory (PCM) has reached the level of mass production.The first step in mass production is determining the proper pulse conditions of high-resistance (HR) and low-resistance (LR) states to realize the best performance of PCM chips on the basis of longer endurance characteristics.However,due to the neglect of each of the relations as well as the square term of each relationship for pulse conditions,the standard screening method for pulse conditions cannot accurately determine the optimal pulse conditions.A new statistical prediction method based on regression analysis is presented in this work.The method can model and predict the optimal pulse conditions of PCM chips on the basis of longer endurance characteristics.In the method,the parameter estimates,model equations and surface plot are generated by the least-mean-square (LMS) method for the regression analysis;the prediction model is established by monitoring the distributions of the resistance values collected from a 4 Kbit block of the 4 Mbit PCM test chips in 40 nm complementary metal oxide semiconductor (CMOS) process.

The crystallization characteristics of a ubiquitous T-shaped phase change memory (PCM) cell, under SET current pulse and very small disturb current pulse, have been investigated by finite element modelling. As analyzed in this paper, the crystallization region under SET current pulse presents first on the corner of the bottom electron contact (BEC) and then promptly forms a filament shunting down the amorphous phase to achieve the low-resistance state, whereas the tiny disturb current pulse accelerates crystallization at the axis of symmetry in the phase change material. According to the different crystallization paths, a new structure of phase change material layer is proposed to improve the data retention for PCM without impeding SET operation. This structure only requires one or two additional process steps to dope nitrogen element in the center region of phase change material layer to increase the crystallization temperature in this confined region. The electrical-thermal characteristics of PCM cells with incremental doped radius have been analyzed and the best performance is presented when the doped radius is equal to the radius of the BEC.

The cycle operation was performed on 1325 phase change memory (PCM) cells, and 4% of these cells could not be RESET to the high-resistance state after 106 cycles. The grown grains have been found in the TEM images, and the heat electron contact (HEC) has laterally diffused. The energy-dispersive X-ray spectroscopy profiles of HEC expound that Si and O elements have both multiplied. Thus, the HEC resistance has increased, resulting in insufficient RESET current. According to measurement, the HEC resistance increased from 4.6 to 7.2 $\text{K}{\Omega }$ after 106 cycles, which would decrease the RESET current from 0.7 to 0.45 mA. Compared with the endurance characteristics of the HEC and PCM device, the PCM device, with an increased HEC resistance, cannot be fully operated. When the HEC resistance is large enough to reduce the RESET current to 0.55 mA, the PCM device would be stuck to set.