Design of a major difference based on the four-quadrant NMOS analog multiplier.The multipliers take the form of a voltage output but not resistance.The simulation is based on Smic0p18um EEROM 2P4M SPICE simulation model and a single 3.3V power supply.It is used Spectre to simulate and providing the simulation results.

With the continuous development of integrated circuits and the continuous improvement of comprehensive level of integrated circuits,noise performance for the growing influence of integrated circuits,so,dealing with the noise has become an issue can not be ignored.This article,based on practical experience in IC design,summarized that in the schematic and layout design of integrated circuits,reflections on the noise problem and some treatment methods.

In this paper,we analysis a RC oscillator to generate a certain frequency waveform.This circuit also has a duty cycle modulation circuit to increase the duration of the high voltage level.the oscillator eventually produce a fixed frequency of 750 Hz.this overcome the disadvantages of variable frequency with instable voltage and fixed duty cycle.

The relationship between noise and capacitance,and the method of decrease noise are discussed and the capacitance is calculated base on the noise by a example of 10 bits ADC.The quantization noise and thermal noise are the basic noise source of ADC.The quantization noise effect the resolution.The thermal noise restrict the signal noise ratio,it is the neck of the high resolution design.Increasing capacitance can decrease the thermal noise.

In this article,from the device's structure and manufacturing the second breakdown of the anti-burnirg power switching transistor was discussed and a new type of high-power transistors was introduced,which has the guidance mean to the vote production.

In this study,first,the background and the physical mechanism of hot-carrier effects will be simply discussed.Then,a simplified model,Hu model,was presented to extrapolate the HCI lifetime of MOSFET(Metal Oxide Semiconductor Field Effect Transistor).Based on this work,we can find optimization method to improve the HCI lifetime of MOSFET.

In this paper,a operational amplifier with rail-to-rail input stage is presented,which adopts a novel kind of current fold cascade circuit as gain stage.It uses current compensation at input stage,which makes transconductance nearly constant.It typically dissipates a power less than 180uw at 3V Vdd.The amplifier achieves an open-loop gain and a unit gain bandwidth higher than 75dB and 1.5Mhz when drive a 5p capacitive load.

In this paper,a novel high precision CMOS bandgap voltage reference which uses a negative back circuit and a RC filter to enhance the PSRR is proposed.Using 1.2 μm BiCMOS process of Beiling,Shanghai,this bandgap voltage reference was designed and simulated.Cadence Spectre simulation results show that this circuit has higher precision and stability,and the output of the bandgap voltage is 1. 254 V.The greatest skew of reference voltage to input voltage is 0.012 mV in the power supply range from 2.7 V to 5.5 V,and the maximum static current of reference is 11.27 μA;the greatest skew of reference voltage to temperature is about 1 mV in the range of-40 ℃～120 ℃;the total current of the bandgap reference is about 10.6 μA with the power dissipation about 38.16 μW at 3.6 V power supply.This bandgap reference also has higher than 100 dB PSRR at low frequency,and the start up time of output is about 39 μs.

文章阐述了梳状数字滤波器的基本工作原理,分析了梳状滤波器的基本结构,提出了一种简单的级联积分梳状数字滤波器(cascade integrated comb dignal filter,CIC DF)的实现方法,减小了芯片的面积.描绘出了系统的信号流图,并对信号流与控制流的工作时序进行了详细的分析说明.在此基础上,运用MATLAB系统工具建立了系统的模型,并完成了系统仿真验证.在电路级完成了verilog语言描述,同时运用modelsim对电路进行仿真验证.

VUMOSFET is a new type of power devices,it is a very important advantage is its unique structure of the trench to reduce the device parasitic capacitances,and parasitic capacitances of the charge-discharge process is to limit the VUMOSFET a major factor in switching speed.This article analyzes the major parasitic capacitance in VUMOSFET structure and the formula given by it can reduce the parasitic capacitances quantitative,thus reducing the switch time to reduce the power loss,it is guide for the design.

A single stage fully differential operational amplifier was designed in SMIC 0.18 μm mixed signal CMOS technology with 3.3 V power supply.The designed Op Amp utilizes gain boosting technique.The main Op Amp is a fully differential folded cascode Op Amp with switched capacitor CMFB.Two simple continuous time CMFB Op Amps are used as auxiliary Op Amp to increase the open loop gain of the main Op Amp.The simulation results show that the designed Op Amp achieves a DC gain of 110 dB with a unity gain frequency of 5 MHz.

With strip-shaped low voltage VUMOSFET cell as an example,characteristics of each component of on-resistance were analyzed systematically.The relationship between specific on-resistance and horizontal vertical structural parameters was qualitatively analyzed.Through analysis and simulation,strip-shaped gate structure of VUMOSFET cell was optimized.

A detection circuit simulated in 1.2 μm BiCMOS process is presented,which can indicate whether the received signals are valid RS-232 voltage levels or not.The circuit includes Schmitt cell,NOR gates and an improved capacitance charge/discharge cell which can produce 30 μs delay.Although the circuit is simple,its function is powerful.Within 30 μs,if there have been invalid RS-232 receiver voltage levels,the detection circuit will output a low level which is sent to the inner of the chip and can be used to shut down the transmitter and charge pump,saving power dissipation.

Based on the elliptic shape characteristic of metallurgical junction boundary formed by lateral diffusion and vertical diffusion,the surface electric field distribution with a single floating field limiting structure is discussed.The analytical expressions about surface electric field intensity and voltage undertaken by main junction and ring junction are presented.According to the critical field approximation at breakdown for a cylindrical junction,the optical design way with ring spacing is researched.The curve of absolute value about surface electric field intensity between main junction and ring junction is approximately parabola.The maximum field is situated in main junction,maximum field increases with the increase of ring spacing and decreases with the increase of lateral diffusible depth.The maximum field on the right of ring junction decreases with the increase of ring spacing and lateral diffusible depth.When maximum field of main and ring junction are simultaneously equal to the critical electric field intensity,the breakdown voltage approaches the maximum value and the corresponding ring spacing is optimum.

A traditional Bandgap Reference Circuits could produce a reference voltage whose temperature coefficient is about 15 ppm/℃.In a circuit,the positive temperature coefficient has a close relationship with the branch circuit currents.The circuit presented in this paper produces a reference voltage of which the temperature coefficient is about 3 ppm/℃ by adjusting the values of the branch circuit current when the temperature ranges from-30 ℃ to 110℃.

The necessities of ESD protection circuits between VDD and VSS are analyzed and the operation mechanism of the VDD-to-VSS ESD protection circuit with the gate-coupled NMOS is also discussed.Based on this structure,a relevant layout design is proposed.The simulation shows that ESD failure voltage is higher than 3 kV.

The relationship between the specific On-resistanceand structure parameters is systematically aralyzed in this paper,and a new-functional physical analytical model of the bar gate structure VDMOSFET is described in detail.This model is not only propitious to the study and produce of specific devices because it is clear in physics concept,but also simple and practical.

In this paper,the importance of functional verification is analyzed and then the design of the CIU96B IP core is also discussed.Based on these research,a relevant testbench design is proposed.The simulation shows that the testbench in this paper realize the verification of the IP core,and is of great help in the design of the IP core.

The design of 60 voltage VDMOS which has 10 mΩ on-resistance is optimized.The detailed data and the optimal design of epitaxial layer risistivity,the thickness of epitaxial layer,unit cell size and so on are provided.The termination theory and design of poly field plate are introduced which makes the device satisfy target require and decreases production cost.

The design thought of rising figure of merit for low voltage UDMOSFET is put forward,and on basis of which certain effect having on the device structure is analysed,for example,the balance between special resistant and break down voltage;the design consideration of parasitic capacitance;even getting optimum area.At last,under the condition of 20V/10A,derivation and calculation at length to the structural design of UDMOSFET are also given.