This article presents an ON-chip fast signal generator and a successive-approximation-register (SAR) analog-to-digital data converter (ADC) for silicon photomultiplier (SiPM) readout applications. The high-pass filter (HPF)-based fast-signal generator sharpens the rising edge of the standard SiPM output signal reducing time jitter due to the dark counts of the detector. It is implemented by leveraging the equivalent resistance of the current mirror transistor and the ac-coupling capacitor between the current mirror and the current discriminator to avoid hardware and power consumption overhead. Compared with OFF-chip solutions, the ON-chip approach eliminates the packaging pins and high-speed buffers needed for carrying the fast signals reducing packaging complexity and power consumption of the readout system. The energy quantizer utilizes the SiPM charge integrator as the ADC track-and-hold (T/H) circuit to improve the front-end power efficiency. The fast signal generator and the SAR ADC are implemented in a current-mode application-specific integrated circuit (ASIC) designed in a 0.18- $\mu \text{m}$ CMOS technology. Measurement results show that the ON-chip fast signal generator is effective in improving the timing performance of the readout system. The timing resolutions are measured using SensL’s $3\times $ 3 mm2 SiPM device with a terminal capacitance of 850 pF using an ultrashort laser pulser. Measurement results show that the fast signal generator improves the timing resolution by 23.4% compared with timing measurement using the standard output signal when the output charge is 300 pC. The ASIC achieved a measured ADC signal-to-noise-distortion ratio (SNDR) of 53.08 dB and a spurious-free dynamic range (SFDR) of 62.74 dB at 1 MS/s and a maximum front-end gain nonlinearity of 3.3% over 20–800-pC input charge range while dissipating 4.1 mW of power from a 1.8-V supply.

This article presents a 5-GS/s 6-bit flash analog-to-digital converter (ADC) in a 28-nm fully depleted silicon-on-insulator (FDSOI) CMOS process. The ADC jointly employs partially active second-stage comparison and $2\times $ time-domain latch interpolation (TDI) to reduce power consumption and avoid extensive calibrations. To enhance the conversion speed of the second-stage structure, the stringent timing constraint is resolved by a 25%–75% duty-cycle clock scheme, a 0.5-bit redundancy in the first comparison stage, and an embedded second-stage slice selection logic. The bandwidth requirements of the track-and-hold (T/H) and T/H buffer under the 25%–75% duty-cycle clock are analyzed. An on-chip successive-approximation (SA)-based comparator offset calibration scheme utilizing FDSOI back-gate bias is also developed, providing sufficient calibration range without impairing comparator speed. The measured prototype achieves a signal-to-noise and distortion ratio (SNDR) of 32.8 dB and a spurious-free dynamic range (SFDR) of 41.82 dB at Nyquist frequency while consuming 15.07 mW power, translating into a Walden figure-of-merit (FOM) of 84.5 fJ/conversion-step.

This paper presents a 6-bit 20 GS/s 2-way time-interleaved (TI) flash analog-to-digital converter (ADC) in a 28-nm FDSOI CMOS technology. Leveraging threshold voltage control via back-gate bias in FDSOI, an automatic comparator offset calibration scheme is developed, which does not require extra transistor pairs or capacitive loads in signal path, thus avoiding comparator speed degradation. To alleviate channel mismatch-induced errors in highly interleaved structure while maintaining a reasonable power efficiency, the ADC adopts a two-way TI structure with the subADC working at 10 GS/s. To further improve the ADC power efficiency, a 1-bit voltage-domain interpolation is utilized. The proposed flash ADC achieves a SNDR of 31.2 dB at Nyquist frequency with a power consumption of 204 mW, translating into a figure-of-merit (FOM) of 344 fJ/conv.-step.

This paper presents a backend machine learningbased nonlinearity calibration scheme for a coarse-fine two stage SAR-TDC hybrid ADC. Different from conventional approaches, the machine learning-based nonlinearity calibration scheme avoids the on-chip pseudonumber (PN) generator or complex, specific matrix operations in the digital domain backend process. The scheme utilizes a two-layer neural network to extract and compensate the bit-weight error caused by circuit nonlinearities such as inter-stage gain error or time-to-digital converter (TDC) delay cell mismatch. The neural network uses the ADC DNL and INL testing results as training data, thus avoiding additional reference channel or a split ADC structure. A 10-bit 500 MS/s coarse-fine SAR-TDC ADC is designed in 22nm FDSOI technology to validate the scheme. The simulation results show the ADC achieves an SNDR of 57 dB, SFDR of 71.3 dB, and an ENOB of 9.18 bits, corresponding to a Walden FOM of 5.2 fJ/conv.-step after backend nonlinearity calibration.

This paper presents an automatic comparator offset calibration scheme for designing high-speed flash analog-to-digital data converters (ADCs). It leverages the threshold voltage control capability via back-gate in FDSOI CMOS technology and thus does not require extra transistor pairs or capacitive loads, avoiding comparator speed degradation. An automatic calibration approach employing a successive approximation algorithm (SAA) is also developed. The comparator along with the calibration circuit are designed in a 28-nm FDSOI CMOS process. Simulation results show that the design achieves a resolution of 1.84 mV and a calibration range of ±58 mV with a power consumption of 440 μW under a 1V power supply.

This article reports a power-efficient $8\times $ time-interleaved (TI) 2.4-GS/s 10-bit successive-approximation-register (SAR) analog-to-digital converter (ADC). To optimize the circuit design in terms of power efficiency and conversion rate, several enhancement techniques are presented. First, a pre-defined bypass window, introduced by the customized non-binary DAC, is used to modestly reduce the power consumption. Several conversion cycles are skipped as the input signal falls within the bypass window. Second, to enhance the operation speed, two alternate comparators are adopted in each ADC channel, and an opportunistic adaptive comparator offset calibration is proposed to eliminate the conversion rate degradation caused by the dedicated calibration cycle. The comparator offset is calibrated only when the bit bypass is triggered with the calibration step size adaptively set to acquire both fast convergence and small algorithm noise. In addition, the reference voltage of each ADC channel is provided by a pre-charged reservoir to avoid inter-channel crosstalk without the introduction of power-hungry-distributed reference buffers. A test chip is fabricated in a 28-nm fully depleted silicon on insulator (FDSOI) process with a core area of 0.11 mm2, including the reference charge reservoirs. Clocked at 2.4 GS/s, the proposed ADC measures a 49.02-dB signal-to-noise-and-distortion ratio (SNDR) at Nyquist while consuming only 9.8 mW from a 0.9-V supply, thus resulting in Walden and Schreier figures of merit (FOMs) of 17.7 fJ/conversion-step and 159.9 dB, respectively.

This paper presents a quadrature frequency synthesizer (QFS) utilizing a switched-coupled slotted inductor (SCSI)-based voltage-controlled oscillator (VCO) to simultaneously improve the reference spurs and out-of-band phase noise while achieving a wide frequency tuning range for multiband 5G mm-Wave (mmW) applications. The QFS is implemented in a 55 nm CMOS process, achieving a reference spurs of -64 to -72 dBc, an in-band phase noise of -81.7 to -87 dBc/Hz at 100 kHz offset and an out-of-band phase noise of -119.1 to -125.4 dBc/Hz at 10 MHz offset, respectively, over the entire 19.89 to 26.35 GHz frequency locking range. The RMS jitter for a 19.89 GHz carrier is 118.7 fs, corresponding to a jitter FOM of -238.47 dB. The chip occupies a die area of 1.31 × 2.13 mm 2 including the testing pads and dissipates 101 mW of power.

A power-efficient 2.4 GS/s 10-bit time-interleaved SAR ADC is presented. To reduce the power consumption, several conversion cycles are skipped as the input signal falls within a predefined bypass window. To enhance the operation speed, two alternate comparators are adopted in each ADC channel. The comparator offset is calibrated only when the bit bypass is triggered. This eliminates the need of a dedicated calibration cycle and the conversion rate degradation is avoided. The reference voltage of each ADC channel is provided by a pre-charged reservoir to avoid inter-channel crosstalk without introduction of power-hungry distributed reference buffers. Fabricated in a 28 nm FDSOI process, the proposed ADC achieves 49.02 dB SNDR and a Nyquist Walden FOM of 17.7 fJ/conv.-step at 2.4 GS/s.

This paper presents a 500 MS/s 10-bit single-channel SAR ADC with a reconfigurable double-rate comparator for enhanced operation speed. The proposed double-rate comparator effectively eliminates the delay caused by comparator reset from the critical path while consuming less power and reducing the clock frequency by half. A test chip is fabricated in a 28 nm FDSOI technology. Clocked at 500 MS/s, the proposed ADC achieves a SNDR of 52.7 dB and a SFDR of 62.49 dB at Nyquist with a power consumption of 1.18 mW, showing a Walden FOM of 6.7 fJ/conv.-step.

This paper presents an integer-N quotient frequency synthesizer (QFS) for V, E, and W multiband millimeter-wave transceiver applications. Design considerations of passive and active components to improve tuning range and phase noise of LC-VCO are presented. A complementary dual-injection injection-locked divider (ILFD) structure with independent gate biasing is proposed to improve injection efficiency and frequency locking range. A pseudo-differential cascode buffer structure is developed to improve the stability of the VCO buffer. The QFS is fabricated in a 0.13 μm CMOS process, achieving a wide frequency range of 27.38 to 33.5 GHz while drawing 70mA of current. At 27.4 GHz, the measured closed-loop phase noises are −80.2, −111.3 and −125.5 dBc at 1, 10 and 100 MHz offset, respectively.

This letter presents a partially interleaved 1-GS/s 8-bit two-step SAR ADC for low-power operations. A fast noise-reduction technique is proposed to increase the power efficiency without significant degradation of the conversion rate. A modified StrongARM latch is adopted to further reduce the comparator noise. A calibration procedure runs in the background to address the nonuniform comparator offsets and the interstage gain error. Fabricated in a 28-nm FDSOI process, the prototype ADC achieves an SNDR of 46.65 dB at Nyquist with a power consumption of 2.1 mW, leading into a Walden FOM of 12.01 fJ/conv.-step.

This paper presents a successive-approximation-register (SAR)-assisted time-interleaved digital-slope analog-to-digital converter (ADC), which takes advantage of both moderate conversion speed of the SAR ADC and low noise of the digital-slope ADC. A coarse SAR ADC is pipelined with 4 channels of digital-slope fine ADC through passive residue transfer for speed, precision and power optimization. A charge sharing-based implementation of the digital-slope ADC eliminates the need for power-consuming on-chip reference buffers. A compact bootstrapped switch-based chopper is proposed to minimize the hardware overhead. Designed and simulated in a 28 nm FDSOI CMOS technology, the proposed ADC achieves a SNDR of 63.74 dB at 500 MS/s while dissipating 2.4 mW, leading to a FOM of 3.83 fJ/conv.-step.

This paper presents a low-power silicon photomultiplier (SiPM) readout front-end with on-chip fast pulse generation and successive-approximation-register (SAR) ADC. The front-end mainly consists of a current buffer with an on-chip C-R high pass filter (HPF), a charge integrator, a current discriminator, and a 10-bit low-power SAR ADC. The current-mode buffer offers a low input impedance thus achieving a high input bandwidth. The on-chip HPF shortens the width of the SiPM's long-tailed single photo-electron (SPE) response to generate the fast pulse signal, which allows the current discriminator to suppress the uncertainty of timing measurement and helps to achieve a better coincidence resolving time (CRT). Compared with off-chip fast pulse generators, no additional I/O pin is required facilitating compact multi-channel SiPM readouts. By reusing the charge integration capacitor as the sampling capacitor of the SAR ADC, the power-hungry charge sensitive amplifier (CSA) is eliminated. The front-end is designed in a 0.18 μm 1P6M standard CMOS technology, and has a low power consumption of 4 mW. The on-chip HPF reshapes the long-tailed SPE pulse width from 50 ns to 3 ns. At 1 MS/s, the SAR ADC consumes 132 μW from a 1.8 V supply, and achieves a SNDR of 58.11 dB and a SFDR of 72.47 dB, respectively.

This paper presents a 25-GS/s 4-bit flash analog-to-digital converter (ADC) designed in a 28 nm FDSOI CMOS process. A comprehensive analysis of the track-and-hold (T/H) bandwidth requirement is performed, providing design guideline for a single-core ADC targeting the leading-edge speed performance. A 1-to-2 StrongArm latch based demux comparator structure with a fat tree thermometer code-to-binary code encoder and body biasing in FDSOI are utilized to reduce the power consumption. The ADC achieves a SNDR of 19.48 dB near Nyquist and dissipates 440 mW of power.

This paper presents a current reuse wideband complementary noise and distortion canceling low-noise amplifier (LNA) for high-frequency ultrasound imaging applications. A single-ended current-reuse LNA structure with low-voltage power supply is utilized to achieve low power consumption. The LNA employs a shunt-feedback feedforward noise canceling technique to accomplish both low noise figure (NF) and wideband impedance matching. A complementary CMOS topology is also exploited to cancel the even-order harmonics to enhance the linearity. The LNA is designed for 30120 MHz high-frequency ultrasound imaging systems, and is implemented in a 180 nm CMOS technology. The LNA achieves a 2 dB NFmin, a 23 dB voltage gain, and a -56 dBc total harmonic distortion (THD) while dissipating 9 mW of power from a 1.3 V power supply.

This paper presents a 12.5 Gbps serial link transmitter application-specific integrated circuit (ASIC) designed in a 65-nm CMOS technology. The ASIC mainly includes an LC-VCO phase-locked-loop (PLL), a 16:1 serializer and a CML driver. Simulation results show that the PLL achieves a 7-to-14 GHz frequency tuning range and an RMS jitter of 0.4 pS. The serializer has a deterministic jitter of 9 pS and a programmable output swing from 200 mV to 1.0 V. The PLL and the serializer consumes 39.6 mW and 73 mW from a 1.2 V power supply, respectively.

This paper presents a 10-bit 250-MS/s time-interleaved pipelined analog-to-digital data converter (ADC). A distributed clocking scheme is developed to eliminate timing skew between channels without introducing load capacitance to the driving buffer of the ADC. The channel offset and gain mismatch errors are calibrated in digital domain. In addition, a switch-embedded opampsharing technique is developed to reduce the ADC power consumption and eliminate the memory effect. The simulated SNDR and SFDR are 61.84 dB and 78.2 dB, respectively. The ADC core consumes 28 mW under a 1.8 V supply at 250 MS/s sampling rate.

This paper presents a 14-bit 2.5 GS/s current-steering digital-to-analog converter (DAC) in 65 nm CMOS. Small transistors are utilized in this design to reduce the 3rd-order harmonic distortion caused by finite output impedance. However, the adoption of small transistors increases the 2nd-order harmonic distortion and degrades the spurious-free dynamic range (SFDR). Hence a digital pre-distortion (DPD) scheme is proposed for 2nd-order harmonic distortion cancellation. In addition, techniques including dynamic element matching (DEM), double-data-rate (DDR) quad switch and always-on cascode switch are employed in this design to further enhance the SFDR. Simulation results show > 70 dB SFDR for input frequencies from 34 MHz to 1.2 GHz. The DAC consumes 375 mW from a dual 1.2/2.5 V power supply.

In this paper, we present a dual-channel serializer ASIC, LOCx2, and its pin-compatible backup, LOCx2-130, for detector front-end readout. LOCx2 is fabricated in a 0.25-μm Silicon-on-Sapphire CMOS process and each channel operates at 5.12 Gbps, while LOCx2-130 is fabricated in a 130-nm bulk CMOS process and each channel operates at 4.8 Gbps. The power consumption and the transmission latency are 900 mW and 27 ns for LOCx2 and the corresponding simulation result of LOCx2-130 are 386 mW and 38 ns, respectively.

This paper presents a high-speed and power-efficient successive-approximation-register (SAR) analog-to-digital converter (ADC). A dual-DAC architecture is proposed to enhance the conversion rate by decreasing the worst-case logic delay and thus the time needed for each conversion cycle. A 1-bit redundancy is introduced to absorb the decision errors caused by the mismatch between the two DACs and to relax the DAC settling requirement. In addition, an addition-only digital error correction technique is utilized to convert the non-binary codes into binary ones. A 10-bit SAR ADC is designed in a 28-nm FDSOI CMOS technology. The ADC achieves a signal-to-noise-plus-distortion ratio (SNDR) of 59.69 dB at the Nyquist input frequency, while consuming 1.53 mW from a 1.0 V power supply at 400 MS/s. The resulting figure-of-merit (FOM) is 4.86 fJ/conv.-step.