Spin-transfer torque MRAM (STT-MRAM) is a promising technology for scaling GPU L2 caches thanks to its high density and near-zero leakage power. However, its high write latency and energy make simply replacing SRAM with STT-MRAM unattractive under the massive write traffic and concurrency of modern GPUs. This work observes that GPU writes exhibit strong coarse-grained spatial locality, such that cache blocks mapped to the same region tend to share similar write intensity. Motivated by this insight, we propose Region-Level Write-Intensity Prediction (RWIP) for GPU L2 cache based on hybrid-retention STT-MRAM. The L2 cache is partitioned into a low-retention (LR) region for write-intensive data and a high-retention (HR) region for read-dominant and long-lived data. RWIP instantiates a lightweight per-subpartition Region Predictor Table (RPT), which is accessed only after a write miss in both the LR and HR regions. RWIP leverages early region-level write activity to predict the write intensity of incoming cache blocks, thereby proactively allocating write-intensive blocks into the LR region. On average, compared to baseline GPU with SRAM-based L2 cache and the prior typical work, RWIP improves instructions per cycle (IPC) by 19

Leveraging the robustness of DNNs, fixed-point mixed-precision models have effectively reduced hardware costs in edge in-memory accelerators. However, existing studies on multipliers are poorly suited to mixed-precision models. On the one hand, most of them employ fixed bit-widths or offer only limited configurations, lacking the fine-grained reconfigurability required by mixed-precision models. On the other hand, layers with smaller retained bit-widths can tolerate larger multiplication errors to achieve lower hardware costs, as the inaccurate bits are discarded. However, existing approximate multipliers cannot achieve low-cost dynamic error control, resulting in this optimization potential being wasted. To address these issues, this study proposes a fixed-point approximate multiplier with fine-grained reconfigurability. By breaking full multiplication into small 2-bit/3-bit operations and discarding non-critical ones selectively, the proposed multiplier ensures high hardware utilization across varying bit-widths while enabling low-cost fine-grained error control. Building on this multiplier, a DDR5-oriented near-memory accelerator architecture is proposed, incorporating extended DRAM commands and semi-SIMD scheduling schemes. Compared to state-of-the-art PIM architectures, the proposed architecture achieves a reduction of 40.8% in area, 16.3% in power consumption, and 6.5% in latency, respectively.

Design space exploration is essential for optimizing deep neural network accelerators, which face increasing computational and energy demands as model complexity grows. Previous approaches rely heavily on local insights, often neglecting the need for extensive exploration to improve the global perspective. This leads to challenges such as blind exploration and a higher likelihood of getting trapped in local optima. Without dynamic adjustments or adaptive strategies, these methods struggle to navigate large, complex design spaces effectively. In this paper, we propose PRDSE, a design space exploration framework based on reinforcement learning that integrates both intrinsic and extrinsic metrics, guided by prior knowledge. The proposed method incorporates an adaptive adjustment mechanism that dynamically balances intrinsic and extrinsic rewards based on the progress of exploration, improving both search efficiency and optimization performance. Compared to state-of-the-art methods, PRDSE achieves substantial improvements, with latency speedups of up to 3.49x in the cloud environment and 3.43x in the edge environment, respectively. This work demonstrates that PRDSE effectively balances exploration and optimization objectives, providing a more efficient and scalable approach to design space exploration in accelerator design.

The design and optimization of deep neural network accelerators necessitates thoughtful consideration of numerous design parameters and various resource/physical constraints that render their design spaces massive in scale and complex in distribution. When faced with these massive and complex design spaces, previous works on design space exploration confront the exploration-exploitation dilemma, struggling to concurrently ensure optimization efficiency and stability. To address the exploration-exploitation dilemma, we present a novel design space exploration method entitled CSDSE. CSDSE implements heterogeneous agents separately accountable for exploration or exploitation to cooperatively search the design space. In order to enable CSDSE to adapt design spaces with various space distributions and expanding scales, we extend CSDSE with mechanism of adaptive agent organization and multi-scale search. Furthermore, we introduce a weighted compact buffer that encourages agents to search in diverse directions and bolsters their global exploration ability. CSDSE is implemented to optimize accelerator design. Compared to former DSE methods, it achieves latency speedups of up to 15.68x and energy-delay-product reductions of up to 16.22x under different constraint scenarios.

Efficient design space exploration method is crucial for optimizing deep Convolutional Neural Network accelerators, as the large design space comprising hardware architecture and dataflow mapping parameters leads to prohibitive optimization time costs. Prior works employ space compression to improve exploration efficiency but focus only on single layers or partial spaces, failing to prevent expansion as network model depth increases. Therefore, in this brief, we propose the LCDSE framework to address the dilemma of space expansion. LCDSE clusters similar layers into blocks as coarse-grained optimization units to constrain parameters and prune redundant design space. Compared to former frameworks, LCDSE achieves up to 4xdelay speedup, 7.9xenergy-delay-product decrease and 2.5xarea-delay-product reduction along with time cost saving by up to 11.3x, demonstrating its superior optimization efficiency.

The design and optimization of deep neural network accelerators should sufficiently consider numerous design parameters and physical constraints that render their design spaces massive in scale and complicated in distribution. When confronted with the massive and complicated design spaces, previous works on design space exploration suffer from the exploration-exploitation dilemma and are unable to simultaneously assure optimization efficiency and stability. In order to solve the exploration-exploitation dilemma, we present a novel design space exploration method named CSDSE. CSDSE implements heterogeneous agents separately responsible for exploration or exploitation to search the design space cooperatively and introduces a weighted compact buffer that encourages agents to search in diverse directions and bolsters their global exploration ability. CSDSE is implemented to enhance accelerator design. Compared to former methods, it achieves latency speedups of up to 6.1x and energy reductions of up to 1.3x in different constraint scenarios.

Recognizing defects on the steel plate surface has great application potential in the steel manufacturing process. However, it is still challenging to accurately recognize surface defects since most defects only occupy a small area of the whole image and have high similarities to the surrounding backgrounds. To solve the above issues, we propose an attention multi-hierarchical feature fusion network (AMHNet) to recognize defects. First, to better fuse the features from different levels, we propose a skipping attention module to selectively transfer informative features in low-level layers into high-level layers based on the convolutional block attention mechanism. Second, to dynamically fuse multi-hierarchical features, we propose a feature dynamic aggregation gate by gating mechanism to enhance defect-relevant features and suppress useless features. Finally, to verify the effectiveness and advantages of our model, we also collect a new challenging defect recognition dataset called NPU-DRD. Extensive experiments on dataset NPU-DRD show that our AMHNet achieves an accuracy of 97.58% and an AUC score of 97.23%, which are the new state-of-the-art results among existing methods. Our new dataset and source codes are available at https://github.com/Heisenberg828/AMHNet .

Person re-identification (ReID) aims to match a specific person across non-overlapping camera views and has wide application prospects. However, existing methods are still susceptible to occlusion and missing critical parts. Most methods fuse low-level detail features and high-level strong semantic features using feature concatenation or addition, leading to useful information being overwhelmed by a large amount of useless information. In addition, many methods extract spatial context features by designing different blocks but ignore the local channel context features. To relieve these issues, this paper presents an improved interaction-and-aggregation network (IIANet) to learn more representative feature representation. First, to improve model robustness to serious occlusion or missing crucial parts of the target person, we employ a global multi-scale module (MSM) to extract multi-scale features by multi-branch convolution and hierarchical residual connection. Second, to selectively fuse low-level detail features and high-level semantic features effectively, we design a gated fully fusion module (GFFM) to control information transmission and reduce feature interferences in fusing different-level features. Finally, we adopt a channel context module (CCM) to learn channel context information via multi-scale local fusion. Sufficient experiments demonstrate the better performances of our IIANet on dataset Market-1501. The mAP and Rank-1 accuracy of our model reach 84.9% and 94.2%, respectively. Our code is available at: https://gitee.com/bingsfan/iianet/tree/master/

Video person re-identification (V-ReID) can leverage rich spatial-temporal information embedded in sequence data to achieve better accuracy. However, it is vulnerable to the interference of inaccurate and redundant noisy frames in each sequence as well as the background clutter and person-irrelevant pixels in each frame. To solve the above issues, this paper presents an adaptive interference removal framework (IRF) to learn discriminative feature representations by removing various interference. Our IRF mainly consists of two modules including an attention-guided adaptive interference frame removal module (IFRM) and an attention-guided adaptive interference pixel removal module (IPRM). IFRM and IPRM are designed to locate task-relevant keyframes and key pixels, respectively. IFRM adopts the attention mechanism to predict frame-wise scores to characterize the contribution of each frame to the final identification task. IPRM collaboratively utilizes camera identity classification loss, person identity classification loss, target attention loss, and person mask adversarial loss for extracting pure pedestrian representations. A progressive mask augmentation strategy is designed to restrain the data distribution of the generated person masks to further guide model training. Extensive experiments demonstrate that our models outperform state-of-the-art accuracy on seven person ReID datasets.

Customized accelerators for Convolutional Neural Network (CNN) can achieve better energy efficiency than general computing platforms. However, the design of a high-performance accelerator should take into account a variety of parameters and physical constraints. The increasing parameters and tighter constraints gradually complicate the design space, which poses new challenges to the capacity and efficiency of design space exploration methods. In this paper, we provide a novel design space exploration method named ACDSE for optimizing the design process of CNN accelerators. ACDSE implements the adaptive compression mechanism to dynamically adjust the search range and prune low-value design points according to the exploration states. As a result, it can focus on valuable subspace while also improving exploration capacity and efficiency. Additionally, we implement ACDSE to address the problem of CNN accelerator latency optimization. The experiment indicates that, compared to former DSE methods, ACDSE can reduce latency and increase efficiency by 1.39x-5.07x and 2.07x-43.87x, respectively, under the most stringent constraint conditions, demonstrating its superior adaptability to the complicated design space.

Racetrack memory, an emerging low-power magnetic memory, promises a competitive replacement for traditional memory in the accelerators. However, random access in racetrack memory is time and energy expenditure for CNN accelerators because of its large amount of invalid-shifts. In this article, we propose an automatic-addressing architecture that builds a novel data layout to guarantee that the next round of memory access can be always satisfied at the in-situ or rigorously adjacent cells of current round, producing a fully serialized access footprint that can drive instant port-alignment without any invalid-shifts in racetrack memory. By this way, original address-based access degrades to the selections repeated among the three candidates, i.e., one in-situ cell and two neighbor cells. Based on this simplification, a lightweight access management can generate the sequence of one-out-three selections according to the deterministic access behaviors defined by CNN hyper-parameters. The evaluation shows that, when deploying the five popular CNN applications to our architecture, the physical shifts of racetrack is curtailed by 74.64 percent over legacy layout, which achieves 54.2 and 42.1 percent energy reduction on read and write, respectively. A case study of YOLOv2 indicates that our architecture performs 6.503 GOp/J that achieves 18.5x improvement to server-level GPUs.

针对航空航天探测等要求高可靠性、强实时性、低功耗的尖端领域,基于新型的异构多核计算平台对全迁移策略的支持,提出了能耗优化的实时任务调度算法.算法主要分为2部分:负载分配和任务调度.负载分配确定每个任务在不同的处理器集群上工作量的分配比例,并对系统的能耗进行优化.任务调度在负载分配的基础上,采用时间片划分的思想对已分配的任务进行合理调度,保证每个任务都能满足系统约束条件.将此算法与现有的SA算法和Hetero-Split算法进行对比,实验结果显示:此算法比Hetero-Split算法在寻求可行性任务调度方案方面相当,但强于SA算法;在能耗比方面,此算法比Hetero-Split算法在系统总能耗方面有大幅度的降低,降低比率约为23％～24％.

With the continuous improvement of IC manufacturing technology, the interconnection scale of network on chip is expanding constantly, which puts forward higher requirements for system reliability. Based on the analysis of the NoC’s fault models, and the analysis of the fault-tolerant design method, this paper proposes a spatial redundancy technology to overcome the permanent or transient errors on links. If three links in the none-edge node fail at the same time, or two links in the edge node fail at the same time, we backtrack and switch the routing policy between XY routing and YX routing to bypass the failed node. The experimental results show that compared with the original XY-YX fault-tolerant routing algorithm, the network throughput is increased and the global average packet delay is reduced.

Convolutional Neural Network (CNN) accelerator design on resource limited platform faces the challenge of lacking efficient design space exploration (DSE) method because of its huge and irregular design space. Numerous parameters belong to accelerator architecture and dataflow mode jointly construct a huge design space while power and resource constrains make the design space become quite irregular. Under such circumstances, traditional DSE methods based on exhaustive search is infeasible for the non-trivial design space and methods based on general optimization algorithms will also be inefficient because of the irregular distribution of design points. In this paper, we provide an efficient DSE method named ERDSE for CNN accelerator design on resource limited platform. ERDSE is based on reinforcement learning algorithm REINFORCE but refines it to adapt the complex design space. ERDSE implements off-policy strategy to decouple sampling and learning phase, then separately refines them to further improve exploration ability and samples utilization. We implement ERDSE to optimize the computing latency of CNN accelerator for VGG-16 and MobileNet-V3. Under the tightest constraints, ERDSE achieves 1.2x-1.7x (on VGG-16) and 2.3-4.9x (on MobileNet-V3) latency improvement compared with other DSE methods, which demonstrates the efficiency of ERDSE.

The 5G network brings about significant convenience in deploying neural network models to edge devices. However, the flexibility challenges the current generation of neural network architectures that seldom involve the target platform as the bounds during the structure searching. The difficult deployment is rooted in the hidden resource provision of the target devices during the SW/HW joint tuning, leading to mismatching between network models and system configuration. This work proposes a scalable neural network search service in the 5G environment to support a continuous knob of the network scales, by which the channel groups can overlap with each other to share the features with continuous coverage. It is proved that the proposed dimension of network scaling provides good predictability of the model performance on specific platforms, which can be further utilized to simplify the regular network architectural search procedures. Then we design a SW/HW co-design workflow that involves both the cloud and edge to fully utilize computing resources on target platforms, meanwhile keeping the network size as small as possible to save the provision of resources. The experimental results show that, with our scalable search service, the key metrics of the network model enjoy a continuous, monotonic, and linear function to the proposed hyper-parameter. The deployment to the Raspberry Pi board shows that the proposed method accurately controls both precision and size of the models; meanwhile, the corresponding search workflow successfully finds the proper network scales with 65 percent reduction of the NAS routines.

High dependability computer system plays an important role in space application under space radiation environment. Registers in CPU (Central Processing Unit) and memory unit are the critical components of computer system security and the sensitive area of soft error. To assess the reliability of a safety-critical system, injecting random faults into these soft errors sensitive areas of the system to observe the behavior of the faulty system is a fast and effective method. In this paper, we present an efficient automated fault injection system FIG-QEMU (Fault Inject by GDB for QEMU) that simulates a variety of Single event effects, including Single event upset. The proposed system can assess not only the sensitivity of various space applications to soft errors, but also the robustness of the operating system. Our results show that 6.21% of the 5 million register faults and 3.53% of the 1.2 million memory faults will cause system crash respectively.

The expansion and improvement of synthetic aperture radar (SAR) technology have greatly enhanced its practicality. SAR imaging requires real-time processing with limited power consumption for large input images. Designing a specific heterogeneous array processor is an effective approach to meet the power consumption constraints and real-time processing requirements of an application system. In this paper, taking a commonly used algorithm for SAR imaging—the chirp scaling algorithm (CSA)—as an example, the characteristics of each calculation stage in the SAR imaging process is analyzed, and the data flow model of SAR imaging is extracted. A heterogeneous array architecture for SAR imaging that effectively supports Fast Fourier Transformation/Inverse Fast Fourier Transform (FFT/IFFT) and phase compensation operations is proposed. First, a heterogeneous array architecture consisting of fixed-point PE units and floating-point FPE units, which are respectively proposed for the FFT/IFFT and phase compensation operations, increasing energy efficiency by 50% compared with the architecture using floating-point units. Second, data cross-placement and simultaneous access strategies are proposed to support the intra-block parallel processing of SAR block imaging, achieving up to 115.2 GOPS throughput. Third, a resource management strategy for heterogeneous computing arrays is designed, which supports the pipeline processing of FFT/IFFT and phase compensation operation, improving PE utilization by a factor of 1.82 and increasing energy efficiency by a factor of 1.5. Implemented in 65-nm technology, the experimental results show that the processor can achieve energy efficiency of up to 254 GOPS/W. The imaging fidelity and accuracy of the proposed processor were verified by evaluating the image quality of the actual scene.

设计了一种针对图像处理类应用程序的并行性分类的方法,并使用工具初步实现了对程序的分类.还研究了图像处理算法的并行性.通过对图像处理算法的主要特征进行分析,得出图像处理算法包含多种并行特征的结论,分别从图像处理程序的混合结构的模型,以及程序中的依赖关系和并行特征两方面进行了分析.结合对程序的分类方式,使用LLVM编译架构初步实现了自动对程序中的程序段进行识别其中的分类模式.

Recently developed spin-based, racetrack memory (RM) shows great promise in enabling nonvolatile memory with unprecedented density and energy efficiency. RM-based technology will leverage the power and cost limit of main memory. However, main memory has random accessing patterns and makes racetrack shifting overhead variable that induces an unstable latency. This paper analyzes the shifting features in view of computing architecture by exploring the design space of RM. We propose RM-based pre-shifting and direction optimized policies to reduce the shifting overhead and to achieve a DRAM comparable performance without additional energy and area overhead. Experiments with a wide range of SPEC2006 benchmarks show the proposed methodology outperforms RM-based main memory without pre-shifting by 12% in energy consumption. Compared to DRAM-based main memory of the same capacity, the proposed methodology improves the energy consumption by 53% on average.