In this work we consider the prospect of using resistive memory microcircuits (RRAM, CBRAM) for space applications. Total dose and single event effects in resistive memory test cells and finished CMOS RRAM microcircuits were investigated. We also provide a comparative assessment of typical hardness levels for other types of non-volatile memories such as flash, ferroelectric (FRAM), magnetoresistive (MRAM) memory. We have summarized the data on SEE and TID hardness levels for different types of commercially available non-volatile memories.

In this work we consider possible approaches to microassemblies constructional adaptation of various functional groups and various designs for heavy ion testing. Using power supplies as an example, we present an algorithm that minimizes the loss of samples during test preparation without losing test informativity. In many cases it is preferable to carry out the preparation in collaboration with the device developer.

The aim of the study is to consider the prospects of using resistive memory microcircuits (RRAM, CBRAM) for space applications. Total dose and single event effects in resistive memory test cells and finished CMOS RRAM microcircuits were investigated. A comparative assessment of typical radiative hardness levels for other types of non-volatile memories such as flash, ferroelectric (FRAM), magnetoresistive (MRAM) memory was provided in this study. The main advantages and disadvantages of using various technologies for the manufacture of non-volatile memory microcircuits with increased resistance to ionizing effects are described.

Стандартные методы оценки параметров чувствительности к воздействию тяжелых заряженных частиц (ТЗЧ) путем проведения испытаний с плотностями потока частиц, на порядки превышающими плотности потока в реальных условиях эксплуатации, занижают стойкость микросхем со встроенной коррекцией случайных ошибок. В работе рассмотрен подход к проведению расчетно-экспериментальной оценки стойкости, позволяющий корректно оценивать параметры чувствительности таких микросхем по одиночным радиационным эффектам (ОРЭ) сбоев.

Представлен рациональный порядок записи в ТУ на ЭКБ информации о радиационной стойкости (РС), полученной в ходе испытаний и расчетно-экспериментальных оценок.

This article deals with a study of radiation-induced leakages between n-regions of various types using test structures fabricated according to the 0.18-µm CMOS technology. It is shown that, depending on the radiation exposure dose, the leakages between the n+-regions and the n-well may exceed the leakages between the n+-regions by 3–9 times, which should be taken into consideration when developing radiation resistant VSHICs.

In this work we investigate the influence of various memory chips supply voltage on their sensitivity to the radiation environment. The main physical mechanisms responsible for radiation-induced degradation at nominal, increased, and decreased supply voltage values are discussed. It is demonstrated that, depending on supply voltage value during irradiation and subsequent testing, device's tolerance to data corruption effects in memory circuits, single event latch-up (SEL) and hard errors induced by ionizing radiation can vary significantly. We also give some recommendations to perform radiation tests.

The Keysight B1500A semiconductor device analyzer based measurement system for test memory cells research is introduced. The connection of a device under test is described as well as the full list of the utilized equipment. The features of the Keysight equipment remote control by means of Keysight VISA are demonstrated; code examples in LabVIEW environment are also presented.

During the last decade, multiple new methods of single event upset (SEU) rate prediction for aerospace systems have been proposed. Despite different models and approaches being employed in these methods, they all share relatively high usage complexity and require information about a device that is not always available to an end user.This work presents an alternative approach to estimating SEU cross-section as a function of linear energy transfer (LET) that can be further developed into a method of SEU rate prediction. The goal is to propose a simple, yet physics-based, approach with just two parameters that can be used even in situations when only a process node of the device is known. The developed approach is based on geometrical interpretation of SEU cross-section and an analytical solution to the diffusion problem obtained for a simplified IC topology model. A good fit of the model to the experimental data encompassing 7 generations of SRAMs is demonstrated. (C) 2017 Elsevier B.V. All rights reserved.

ОбзорСхемотехническое моделирование одиночных эффектов при воздействии тяжелых заряженных частиц в КМОП СБИС с суб-100-нм проектными нормами А.А.Смолин 1

The optimal laser wavelengths for transient ionizing response due to dose rate effect simulation of 0.24 um CMOS SOI devices was found to be 0.56 um for top side irradiation and 1.06 μm for backside irradiation.

MRAM cell permanent failures was observed along with SEL under laser and ion beam irradiation. Sample preparation for back side was proposed to safe MRAM functionality and to allow focused laser irradiation though the substrate of MRAM die.

The paper concerns ferroelectric film features and their application in the field of memory ICs design. The results of FRAM test memory cells irradiation are shown and discussed. The current responses of the memory cells are presented as well as the calculated value of polarization The measurement complex used during the experiment is described.

The paper presents experimental data of single event hard errors (SEHEs) in commercial SRAM cells during SEE testing and TID tests. It is shown that the numbers of faulty cells under ion and under gamma irradiations are in qualitative agreement.

The paper presents experimental results of FRAM single event effects (SEE) tests. The dependence of FRAM susceptibility to the Single Event Functional Interrupt (SEFI) and Single Event Hard Error (SEHE) on the operational mode during irradiation was analyzed.

We propose a new semi-empirical method for estimation of Single Event Upset (SEU) cross-section for SRAM Dual Interlocked Cells (DICE) with known distance between neighboring sensitive volumes. The method is based on experimental analysis of SEU maps in sub-100 nm 6T SRAM along with layout considerations and SPICE simulations. It could help to significantly improve SEE robustness of modern CMOS VLSI by design.

This paper presents the results of implementation of National Instrument based system for Single Event Upset testing of memory chips into neutron generator experimental facility, which used for SEU tests for avionics purposes. Basic SEU testing algorithm with error correction and constant errors detection is presented. The issues of radiation shielding of NI based system are discussed and solved. The examples of experimental results show the applicability of the presented system for SEU memory testing under neutrons influence.

The paper discusses the automation of the processing of images obtained with an oscilloscope using National Instruments LabVIEW software. The mathematical background is presented as well as standard hardware communication interface. The block diagram of the electrical signal acquisition and processing system and the front panel with an example of processed waveforms is shown in the paper.