Vertical NAND flash memory cell array by TCAT (terabit cell array transistor) technology is proposed. Damascened metal gate SONOS type cell in the vertical NAND flash string is realized by a unique dasiagate replacementpsila process. Also, conventional bulk erase operation of the cell is successfully demonstrated. All advantages of TCAT flash is achieved without any sacrifice of bit cost scalability.

As device size shrinks smaller, not only random telegraph signal (RTS) noise, which is caused by the trapping and de-trapping of a single carrier but also the degradation of gate oxide due to hot-carrier stress become a serious issue. In this paper, random telegraph signal (RTS) measurements have been used to study individual hot-carrier-induced traps in n-type metal oxide semiconductor field effect transistor (nMOSFETs). Trap depth (xT), lateral location (yT), and trap energy (ECox-ET) of stress-induced traps are founded to be different from those of process-induced traps. Also, we confirmed the hot-carrier stress induced traps are located near drain region.

The interface states have been one of the main reliability concerns for nano-scale metal oxide semiconductor field effect transistors (MOSFETs). Especially, the stress induced interface states generation is very important. For quantitatively clarify, the high-frequency charge pumping technique is presented and it has better accuracy and easier than former charge pumping method, which needs variable rise and fall times of gate pulse. Furthermore, it can reject border traps effect. Using the presented method, the energy distribution of interface states was extracted and the Fowler-Nordheim stress induced energy level of interface states was profiled in pure silicon dioxide and finely engineered remote plasma nitrided oxide. The technique is well suited for investigating the nano-scale MOSFET reliabilities. (C) 2009 The Japan Society of Applied Physics

A novel complementary metal–oxide–semiconductor (CMOS) process compatible and self-aligned fabrication method for the dual-gate single-electron transistor (DG-SET) is presented. The performance of previous versions of the DG-SET was limited by inherent parasitic elements and its fabrication process was divergent from conventional CMOS, limiting the possibility of co-integration. Through simulation, the parasitic elements are confirmed to be caused by the non-self-alignment of the control gate, side gates, and source/drain. To resolve such issues, a new type of DG-SET was fabricated using a self-aligned process. Measurement results obtained at room temperature revealed clear Coulomb oscillation peaks in the trans-conductance curve. Through parameter extraction and its comparison with previous results, this is confirmed to be the consequence of single-electron tunneling. Also, in order to confirm that the single-electron tunneling is caused by the electrically induced tunneling barriers, and not by random fluctuations along the SOI active, low temperature measurement results for devices with different parameters is compared.

We demonstrate a new postmetallization annealing and ultraviolet (UV) treatment process for reducing the dark current of image sensors. The new method utilizes a large amount of hydrogen in a plasma-silicon nitride film (p-SiNx) as a hydrogen diffusion source. Through charge pumping measurement, it is proved that this method effectively reduces the interface trap density of pixel transistors, thereby decreasing the dark current of image sensors. Although the postetch process for removing p-SiNx films induces plasma damage during the etch step, the damage can be effectively cured by the subsequent UV annealing.

A 1.4 μm-pitch pixel of CMOS image sensor, which is the smallest to date, has been successfully developed and integrated into 8M density for the first time. To overcome the crucial degradation of the saturation charge and sensitivity, a novel photodiode structure extended under transfer gate and an elaborate optical design including very thin tungsten pixel routing with 65 nm-grade design rules are introduced, which result in enhanced electrical and optical performance.

Multi-level NAND flash memories with a 38nm design rule have been successfully developed for the first time. A break-through patterning technology of Self Aligned Double Patterning (SADP) together with ArF lithography is applied to three critical lithographic steps. Other key integration technologies include low thermal budget ILD process and twisted bit-line contact for excellent isolation between adjacent bit lines. Hemi-Cylindrical FET (HCFET) together with charge trapping memory cell of Si/SiO 2 /SiN/Al 2 O 3 /TaN (TANOS) was found to be effective in sufficing various electrical requirements of 30nm generation flash cells. Finally, MLC operation is successfully demonstrated with flash cells of 8Gb density in which all the technologies aforementioned are combined.