Lanthanum oxide (LaxOy) and magnesium oxide (MgxOy) high-k cap-dielectrics have been used to modulate the effective work function for high-k/metal gate CMOS devices. The use of DIW during wet processing leads to unacceptable material loss due to the high solubility of materials. In this work, new rinsing procedures with pH-controlled and solvent-based solutions were evaluated in order to avoid material loss. It is validated that both pH-controlled (> pH 10) and solvent-based solutions achieve less than 1 Aå of La2O3 loss and solvent-based solutions can well be used on MgO2, providing less than 1 Aå loss. Furthermore, no adverse affects, such as an increase in particle or surface roughness, were observed by applying the new rinsing procedures.

The introduction of metal gates and high-k dielectrics in FEOL and porous ULK dielectrics in BEOL presents severe issues [1] and leads to the requirement of new chemistries and processes. A major challenge in cleaning is the removal of photoresist (PR) in both FEOL and BEOL. In current semiconductor device fabrication flow, the photoresist strip process in FEOL is mostly achieved by applying a sequence of plasma ashing followed by a wet-clean step with sulfuric-peroxide mixture (SPM). But in general, ashing leads to strong oxidation or etching of silicon substrate. Hence, several approaches for ashless PR strip have been reported, such as hot SPM [2] and the combination of a pre-treatment using high velocity CO2 aerosol [3].

High-k gate dielectrics (HK), such as HfO2 or HfSiON, are being considered as the gate dielectric option for the 45nm node and beyond. In order to alleviate the Fermi-level pinning issue and to enhance the CET (Capacitive Effective Thickness) by generating the depletion layer in poly-Silicon gate, metal gate electrodes with proper work functions (WF) have to be used on the high-k dielectrics.

Strained silicon engineering was first used at the 90-nm node. Nowadays, a series of techniques has seen wide-spread use and many derivatives are available because of their ease of integration and cost-effective features [ , ]. As a main part of stressor technique, embedded SiGe-S/D technology is reported to improve the pMOSFET drive current [ , ].

As the critical dimension of LSI continues to decrease, the surface tension of water and its effect on the formation of watermarks is becoming a significant problem. It is known that watermarks are easily generated when a silicon hydrophobic surface is dried in a wet cleaning process. Many studies about watermarks have been reported [1, 2]. Additionally if the rinse and dry steps were performed under an inert (nitrogen) ambient and the rinse water had low oxygen concentration, watermarks could be effectively avoided [3, 4].

Cleaning of nano-particles is becoming a major challenge in semiconductor manufacturing as efficient particle removal must be achieved without substrate loss and without damage to fragile structures. In this work cleaning performance and structural damage by a mixed fluid-jet technique were evaluated and directly compared to the performance of several megasonic systems. The test vehicles were hydrophilic Si wafers contaminated with 78-nm SiO2 particles and 70-nm poly-gatestack line patterned wafers. The results showed a broader process window for particle removal without damaging for the mixed fluid-jet technique compared to the megasonic systems.

With the continuous shrinkage of critical sizes in semiconductor manufacturing, nano-particles smaller than 100-nm are becoming a potential threat to devices in chips. Storage of wafers contaminated during process steps often results in a decrease of particle removal efficiency in subsequent clean, a phenomenon referred to as aging. In this work, the influence of aging on the removal of silica and silicon nitride nano-particles from hydrophilic Si wafers was studied for different storage conditions. Trends observed for aging as a function of particle size and for different tools indicated that aging will become an issue for critical cleans where substrate etching must be kept very low and the physical component of the clean must be decreased to prevent damage to fine structures. Controlling the relative humidity during storage helped in lowering the effect of aging.

In this work the damage added on gate stack features after batch megasonic cleaning is identified and classified by SEM review. To understand if damaging is a random or a clustered process, damage clustering distributions are compared with a theoretical random distribution of damage sites. In the damaged areas, defect clusters are observed that we explain by the presence of so-called weak spots in the neighborhood of a damaging event. Only a limited influence of the megasonic cleaning settings was found on the damage-size distributions. This suggests that, for the cleaning conditions investigated in this work, the number of added defects varied with the amount of the damage events but the event strength remains the same.

Epitaxial deposition of strained Si and SiGe to improve electron and hole mobility and Vt shift is becoming more and more part of the standard CMOS processing [1,2]. One of the most important restrictions imposed on advanced CMOS processing is that on thermal budget. For epitaxial growth processes this thermal budget is quite high. The main contribution comes however not from the growth itself, but from the in-situ H2 bake necessary to remove any oxide traces left prior to epi. Without any pre-epi etch, removal of the native oxide requires at least a bake for several minutes at 900 ̊C or higher. When combined with a wet clean which removes the native oxide and passivates the surface (usually H or Cl), this temperature can be reduced to the range of 850-750 ̊C, although this is always at the cost of a remaining C and O peak at the epi-substrate interface.

Cleaning technologies employing physical forces (such as megasonic and high-velocity-aerosol cleaning) are usually evaluated by comparing the particle removal efficiency on blanket wafers with damage formation on fragile structures, typically gate stack type structures. However patterned wafers provide a much more realistic cleaning challenge. Particle removal efficiencies from trenches in micrometer dimension have been evaluated using high-velocity-aerosol cleaning. When using short cleaning times, a large decrease in cleaning efficiency is found for even modest pattern dimension. By extending the cleaning time, cleaning efficiencies comparable to blanket-wafer tests can be reached. Moreover, batch megasonic cleaning shows a similar decrease in performance as high-velocity-aerosol cleaning.

Thisstudy will review someofthecritical aspects ofcleaning forsub-65 nm technologies. Theseissues include: surface preparation forhigh k dielectrics on Siandon Ge,metalgate cleaning andremoval ofsmall particles without creating damage to structures.

Introduction For the past few decades, RCA cleaning, that was developed by Kern, et.al. [1], has been the main method for cleaning wafers of semiconductor devices. SC1 (NH4OH/H2O2/H2O-mixture), which constitutes the first step of RCA cleaning, is one of the most widely used wet chemistries for particle and organic contaminants removal. SC2 (HCl/H2O2/H2O-mixture), which is the second component of the RCA cleaning procedure, removes metal contaminants.