Self-Aligned Quadruple Patterning (SAQP) is used in advanced CMOS-FET technologies to enable the formation of arrays of fins at sub-40 nm pitches. As these technology nodes keep scaling down and the fins get taller for performance improvement, the patterns become denser and present very high aspect ratio (HAR). The scaling trends make the fin pattern more subject to mechanical instabilities during the processing steps. We describe in this paper a specific mechanical fin bending mode linked to the SAQP scheme targeting 24 nm pitch, the HAR and the formation and recess steps of the isolating oxide. We investigated the evolution of fin bending throughout the fin and isolation formation. We observed fins start bending at the FCVD deposition step exhibiting rotation angles up to 3 degrees. The bending was then worsened along the subsequent process steps causing mechanical failure after fin reveal where up to 7-8 of bending angles were observed. After having studied the influence of the key process steps, we can report a path to mitigate this phenomenon. Finally, we propose a simple mechanical analysis to validate quantitatively the root cause and extrapolate the mechanical robustness of this system for further scaling nodes where fin pitch is reduced.

EUV resists, while improving steadily, generate a number of nanobridge or break defects that increases quickly as the pitch approaches 30 nm. Inline inspection methods are therefore needed to reliably detect patterning defects smaller than 20 nm. Massive e-beam metrology provides the high resolution needed to measure these defects, while remaining compatible with HVM throughput requirements. In this work, we used a direct metal (Ru) etch process, to fabricate EUV-patterned electrical structures in the 32 nm-36 nm pitch range. We demonstrate an almost one-to-one correspondence between the e-beam metrology yield of the structures, and their electrical yield. The e-beam inspection is realized with a large-field-of-view HMI eP5 e-beam system. The match between e-beam and electrical yield shows that our e-beam inspection is able to catch all electrically relevant line breaks, while excluding false flags. These results demonstrate the capability of massive e-beam inspection in predicting electrical yield.

Continued improvement in pattern fidelity and reduction in total edge placement errors are critical to enable yield and scaling in advanced devices. In this work, we discuss patterning optimization in a combined two-layer process, using ArFi self-aligned double patterned line and EUV via process in a 10nm test vehicle. In prior work (1), we showed the composite correction ability for lithography and etch systems in single layer processes. Here, we expand on the optimization and setup to improve the single layer process, improve the line edge roughness, and look at a second layer via process. The sum of all those optimizations is the edge placement. Here, we describe the fidelity of the final multilayer pattern and the process budget for a two-layer line and via process in terms of total edge placement error (EPE) (2). In the line process, control of mechanical interactions in the resist and etch process significantly improve line width and line edge roughness (LWR/LER), with a net improvement in LWR of 30% measured after develop, and 18% measured after etch. Pitchwalk is improved using cross wafer etch and litho co-optimization to less than 1.0nm 3 sigma. For the via process, we determine the root distribution of EPE resulting from the core placement errors at lithography and etch. Results on final multilayer pattern uniformity, overlay, and edge placement are shown.

With shrinking design rules, the overall patterning requirements are getting aggressively tighter and tighter. For the 5-nm node and beyond, on-product overlay below 2.5nm is required. Achieving such performance levels will not only need optimization of scanner performance but a holistic tuning of all process steps. In previous work, it has been shown that process-induced pattern asymmetry has significant impact on overlay performance at wafer edge and can be partially compensated by applying high-order scanner corrections or optimizing metrology targets. Today, we present the reduction of process-induced pattern asymmetry in a tunable etch system and demonstrate the related on-product overlay improvement combined with scanner corrections.In our work we utilize etch tools (Lam Kiyo (R) conductor etch systems) with proprietary edge tuning technology that can be used to reduce the etch-related asymmetry at the wafer edge. In combination to this unique method, we evaluate the impact of high order corrections per exposure field to compensate for process asymmetry at the wafer edge with a stateof-the-art 1.35 NA immersion scanner (NXT: 1970Ci).The study is done on dedicated test wafers with 10-nm logic node design. We use angle-resolved scatterometry (YieldStar (R) S-250), atomic force microscopy, and SEM cross-sections to characterize process asymmetry. We present experimental investigation of the effect of etch tuning and scanner corrections on the pattern shift and the resulting overlay. In particular, we present results showing a reduction of etch-induced pattern shift by 12nm at wafer radius 147mm.Results show that asymmetry can be addressed by both, litho compensation and etch tuning, and bring on-product overlay down to the required level. We discuss the benefit of the correction techniques especially for thick hard mask layers (the pattern shift scales linear with hard mask thickness) and evaluate a combined correction scenario, where preventive etch tuning and feed-back based scanner corrections are used. We conclude that a holistic tuning of all process steps will be required to fulfill overlay requirements of future nodes.

With shrinking design rules, the overall patterning requirements are getting aggressively tighter. For the 7-nm node and below, allowable CD uniformity variations are entering the Angstrom region (ref [1]). Optimizing inter-and intra-field CD uniformity of the final pattern requires a holistic tuning of all process steps. In previous work, CD control with either litho cluster or etch tool corrections has been discussed. Today, we present a holistic CD control approach, combining the correction capability of the etch tool with the correction capability of the exposure tool. The study is done on 10-nm logic node wafers, processed with a test vehicle stack patterning sequence. We include wafer-to-wafer and lot-to-lot variation and apply optical scatterometry to characterize the fingerprints. Making use of all available correction capabilities (lithography and etch), we investigated single application of exposure tool corrections and of etch tool corrections as well as combinations of both to reach the lowest CD uniformity. Results of the final pattern uniformity based on single and combined corrections are shown. We conclude on the application of this holistic lithography and etch optimization to 7nm High-Volume manufacturing, paving the way to ultimate within-wafer CD uniformity control.

Over recent decades, continuous reductions in the scale of fieldeffect transistors in accordance with Moore’s law, which states that the number of transistors in an integrated circuit doubles every two years, have enabled continuous increases in device performance and transistor density.1–3 Currently, state-of-theart devices are based on structural elements with dimensions of 7nm or even 5nm (N7/N5). The highest-resolution patterns required for N7/N5 devices are silicon fins with a pitch of 18–28nm and metal layers with a pitch of 24–32nm. These dimensions far exceed the resolution attainable with 193 immersion (193i) lithography. Extreme UV lithography might be an alternative process for the formation of lines and spaces, but is expensive and not entirely ready for use in production.4 To overcome the limitations of lithography, multiple patterning methods—litho-etch or self-aligned multiple patterning— were used in the last four stages of device miniaturization based on nodes of 10–28nm (N10–N28).5, 6 To achieve the specifications for fins in N7/N5 devices, we need a self-aligned quadruple patterning (SAQP) method that provides a critical dimension (CD) of about 7nm, a CD uniformity (CDU) and pitch walk of 0.5nm (3 sigma), and a line width roughness (LWR) and line edge roughness (LER) of 1.4 and 1.2nm, respectively. We have developed a low-cost SAQP method that has the potential to meet these requirements for fins. We started with a 193i lithography pattern with a pitch of 90nm and lines and spaces of 40 and 50nm, respectively, which we transferred onto a mandrel. Then we deposited silicon dioxide (SiO2) spacers by Figure 1. Simulation images of the stages of self-aligned quadruple patterning (SAQP) obtained using Coventor SEMulator3D software show, from left to right: patterning of the first core (brown) onto a mandrel (green); deposition of silicon dioxide (SiO2) (light blue) by atomic layer deposition (ALD); etching of the first spacers; etching of the mandrel to produce the second core; further deposition of SiO2 by ALD; and etching of the second spacers and silicon nitride pad (dark blue). The scale bars represent 30nm.

The onset of the 22 nm node introduced three dimensional tri-gate transistors into high-volume manufacturing for improved electrostatics. The next generations of fin nMOSFETs are predicted to be InGaAs based. Due to the ternary nature of InGaAs, stoichiometric and structural modifications could affect the electronic properties of the etched fin. In this work we have created InGaAs fins down to 35 nm fin width with atomic surface structure kept nearly identical to that of the bulk. Our experimental and simulation results show the impact of surface stoichiometry and fin profile on electrical performance.

Amorphous silicon (a-Si) gates with a length of 20nm have been obtained in a ‘line & cut’ double patterning process. The first pattern was printed with EUV photoresist and had a critical dimension close to 30nm, which imposed a triple challenge on the etch: limited photoresist budget, high line width roughness and significant CD reduction. Combining a plasma pre-etch treatment of the photoresist with the etch of the appropriate hard mask underneath successfully addressed the two former challenges, while the latter one was overcome by spreading the CD reduction on the successive layers of the stack.

This paper discusses the approach for patterning 15nm Half Pitch (HP) structures using EUV lithography combined with Self-Aligned Double Patterning (SADP). A stack composed of a double hard mask, which allows decoupling photoresist transfer and trim, and an alpha-Si mandrel, which offers better mechanical properties during the mandrel and spacer patterning, is proposed. A break-down study with the patterning steps was performed to investigate the key contributors for improvement of LWR, LER and CDU, targeting integrated solutions with lithography, etch, thin film deposition, and wet cleans for selected applications. Based on the optimization of these key patterning contributors, optimum LWR, LER and CDU at 15nm HP are demonstrated.

Abstract. The approach for patterning 15-nm half-pitch (HP) structures using extreme ultraviolet lithography combined with self-aligned double patterning is discussed. A stack composed of a double hard mask, which allows decoupling photoresist transfer and trim, and an α-Si mandrel, which offers better mechanical properties during the mandrel and spacer patterning, is proposed. A break-down study with the patterning steps was performed to investigate the key contributors for improvement of linewidth roughness (LWR), line-edge roughness (LER), and critical dimension uniformity (CDU), targeting integrated solutions with lithography, etch, thin film deposition, and wet cleans for selected applications. Based on the optimization of these key patterning contributors, optimum LWR, LER, and CDU at 15 nm HP are demonstrated.

Silicon nano-pillars as test structures for quantitative evaluation of advanced wafer drying are presented. The method consists of the use of pillar structures with an aspect ratio up to 28 in combination with top-down SEM inspection and subsequent image analysis for quantification. The test vehicle allows characterizing cleaning techniques by a threshold aspect ratio below which value the features do not collapse. As such, a higher critical aspect ratio corresponds to a superior wetting/drying method. Furthermore, as the metrology is specific and includes cluster size distribution analysis, it can bring new insights in the mechanism of pattern collapse.

The removal process of the La2O3/HfO2 dielectric and of the residues after metal gate etch are discussed. The challenges are presented and related to the specific physico-chemical properties of La-containing compounds. Solutions based on optimization of plasma etch, strip and wet clean are demonstrated for both an integrated and delayed etch–clean process. Both processes meet the stringent requirements of complete removal of the high-κ layers and metal-containing sidewall residues without inducing silicon recess or undercut.

A dry-wet patterning process for La2O3/HfO2-containing high-κ/ metal gate stacks was successfully developed. The process meets the stringent requirements of complete removal of the high-κ layers and metal-containing sidewall residues without inducing silicon recess or undercut. The interaction between the dry etch and wet clean steps was studied. Use of a BCl3-based plasma process facilitated the cleaning process as it damages and modifies the high-κ layers in the active area. When the dry etch process ends with a BCl3-step, La-containing residues were formed inhomogeneously over the wafer within the time scale of hours. These residues could no longer be removed with a wet clean, but were not observed when the dry etch and wet clean processes were integrated. This demonstrates that an integrated etch-clean process enlarges the process window.

The benefits of integrating wet clean with plasma dry etch processes have been investigated. The studied applications included shallow trench isolation (STI), hardmask-based poly-silicon (poly-Si) gate, and nickel silicide (NiSi) contact etch. In particular, the novel technology Confined Chemical Cleaning™ has been evaluated using diluted hydrofluoric acid or an ammonia hydroxide–hydrogen peroxide mixture at short and controlled exposure times on the order of seconds. It was observed that the ability to remove post-etch residues using the same wet clean process diminished with increasing delay time between etch and clean, in the timescale of hours. In addition, a detrimental effect on the electrical performance was observed for the contact application. As shown, applying stronger cleaning conditions is one solution to remove residues (STI and poly-Si gate) or to restore the electrical performance (contact). However, the more aggressive residue removal process resulted in a higher substrate loss. The mechanism of the delay effect for the poly-Si gate application has been investigated. Evaluation of the post-etch residues using thermodesorption mass spectrometry revealed that post-etch residues were primarily inorganic in nature. Interaction of the post-etch residue and/or substrate with water vapor from the ambient environment is at the origin of the observed delay effects. The mechanism proposed is a hydrolysis of oxychlorine bound in the top layer of the residue, in combination with the dissolution of SiO2 residue material into silicic acid, resulting in a strengthening of the SiO2 network structure and hence increased resistance to wet cleaning. For the contact application, the electrical degradation of the contact resistance under “no clean” or “delayed clean” conditions was correlated with the presence of an oxide layer at the metallic barrier/NiSi interface. This interfacial layer was not present for wafers with the integrated clean, which showed low contact resistances and high yield.

Abstract not Available.

A dry-wet patterning process for La2O3/HfO2-containing high-kappa/metal gate stacks was successfully developed. The process meets the stringent requirements of complete removal of the high-kappa layers and metal-containing sidewall residues without inducing silicon recess or undercut. The interaction between the dry etch and wet clean steps was studied. Use of a BCl3-based plasma process facilitated the cleaning process as it damages and modifies the high-kappa layers in the active area. When the dry etch process ends with a BCl3 step, La-containing residues were formed inhomogeneously over the wafer within the time scale of hours. These residues could no longer be removed with a wet clean, but were not observed when the dry etch and wet clean processes were integrated. This demonstrates that an integrated etch-clean process enlarges the process window.

Recent years have seen a diversification of materials that are used in micro-electronic device fabrication. Initially, the materials were limited to silicon, silicon oxide and silicon nitride. For metallization, aluminum was used. Metal silicides were introduced to lower contact resistance. Later, TiN barriers and W plugs were used, followed by copper metallization and low-κ dielectrics. Currently the very heart of the memory cell and the transistor are being replaced by metallic oxides and metal gate electrodes.

The experimental study of the bonding geometry of a (100)Ge surface exposed to H2S in the gas phase at 330°C shows that 1 ML S coverage with (2×1) surface reconstruction can be achieved. The amount of S on the Ge surface and the observed surface periodicity can be explained by the formation of disulfide bridges between Ge–Ge dimers on the surface. First-principles molecular dynamics simulations confirm the preserved (2×1) reconstruction after dissociative adsorption of H2S molecules on a (100)Ge (2×1) surface, and predict the formation of (S–H)–(S–H) inter-Ge dimer bridges, i.e., disulfide bridges interacting via hydrogen bonding. The computed energy band gap of this atomic configuration is shown to be free of surface states, a very important finding for the potential application of Ge in future high performance integrated circuits.