Tip to Tip (T2T) of interconnect lines in advanced CMOS is quite important when downscaling the area of SRAM and logic standard cells. When T2T size is increasing we have less space for via placement. Additionally variability could impact the yield of the Dual Damascene (DD) structure because of via placement or alignment. As we continue to extend 193i lithography for patterning block using multi-patterning schemes, it is important to understand which processes have the most impact to T2T variability. In this paper we characterize the process window of key steps in a multi-patterning flow using Tone Inversion (TI) by studying the factors affecting CD in a T2T construct with 193i. We run a quantitative process window study of TI flow by using a DOE with emphasis on evolution of T2T dimension all completed on a virtual platform using COVENTOR SEMulator3D® tool. The virtual results were compared with 300mm silicon data processed at IMEC site with good agreement.

The ultra-thin body-bias (UTBB) and fully- depleted silicon on insulator (FDSOI) 28nm technology offers the capability of extreme low power performance, in part because of the use of ultra-thin buried oxide. This unique capability could be jeopardized by the probability of over etching the buried oxide layer during the formation of contacts, with potential generation of electrical short with the substrate. We used SEMulator3D virtual fabrication platform from Coventor to model the contact punch-through mechanism. We then run a design of experiment with the model to quantify the sensitivity of each process variable. Finally we used the virtual fabrication methodology to improve the robustness of the process.

For the first time, WS2-based transistors have been successfully integrated in a 300 mm pilot line using production tools. The 2D material was deposited using either area selective chemical vapor deposition (CVD) or atomic layer deposition (ALD). No material transfer was required. The major integration challenges are the limited adhesion and the fragility of the few-monolayer 2D material. These issues are avoided by using a sacrificial Al2O3 capping layer and by encapsulating the edges of the 2D material during wet processing. The WS2 channel is contacted with Ti/TiN side contacts and an industry-standard back end of line (BEOL) flow. This novel low-temperature flow is promising for integration of back-gated 2D transistors in the BEOL.

For the first time, WS 2 -based transistors have been successfully integrated in a 300 mm pilot line using production tools. The 2D material was deposited using either area selective chemical vapor deposition (CVD) or Atomic Layer Deposition (ALD). No material transfer was required. The major integration challenges are the limited adhesion and the fragility of the few-monolayer 2D material. These issues are avoided by using a sacrificial Al 2 O 3 capping layer and by encapsulating the edges of the 2D material during wet processing. The WS 2 channel is contacted with Ti/TiN side contacts and an industry-standard back end of line (BEOL) flow. This novel low-temperature flow is promising for integration of back-gated 2D transistors in the BEOL.

Process simulations provide vital insights to identify the key process steps to dedicate wafer resources for improvement or to determine investment on tool capability. We considered this problem in the context of an industry-like 5nm Back-End-of-Line flow being developed in IMEC and modeled the approximately 150 step process flow in COVENTOR SEMulator3D®. For the first time a one-million wafer Design of Experiments was conducted to sample a 10-dimensional variable space and derive the failure points for each process parameter. A vector based algorithm was used to search the parameter space and derive a hyper-surface to represent the absolute yield limits. The virtual wafers were run to identify process sensitivities and spec limits for expected process variations. This work highlights that process optimization is needed to improve the capability of many processes to the order of 1nm and this methodology should be used to screen standard libraries for process sensitivities.