We present a novel dual isolation scheme with standard STI and + a single diffusion break local oxidation of the film in FD-SOI technology, extending its highly efficient back-bias capability. For the first time, both Forward and Reverse modes are demonstrated on the same ring-oscillator devices from 28nm FD-SOI technology. A large range of performance/leakage tuning is achieved with record voltage drop across NMOS and PMOS wells ranging [−3V,+5V]. Leveraging this capability, we experimentally demonstrate a process-induced variability reduction of ~50% on Frequency using independent NMOS/PMOS back-biasing in several regimes.

The effect of back-end of line (BEOL) process on cell performance and reliability of Phase-Change Memory embedded in a 28nm FD-SOI platform (ePCM) is discussed. The microscopic evolution of the Ge-rich GST alloy during process is the focus of the first part of the paper. A new metric for quantification of active material modifications is introduced to better follow its evolution with process sequence. Ge clustering has been shown to occur during the fabrication, impacting the pristine resistance and the after forming cell performance. Two different BEOL processes are then benchmarked in terms of key performance. An optimized process is identified, and an extensive electrical characterization of array performance and reliability is done on the full 16MB chip. The optimized BEOL process results in a memory cell fully compatible with the requirements for demanding automotive applications.

One of the most promising Embedded Phase Change Memory (ePCM) integration scheme is the wall architecture, which relies on the dedicated Heater element to thermally switch the device. A good control of this element is a key factor to satisfy the performance requirements of the automotive market. In this paper, the optimization of TiSiN Heater system in $0.019\mu \mathrm{m}^{2}\text{ePCM}$ cell realized with 28nm FDSOI technology is extensively reported. Key fabrication parameters defining heating efficiency are investigated, covering a large range of Heater resistance. Their impact on $e$ PCM reliability of elementary device and 16MB memory array, considering both retention and endurance, is characterized and the key role played by Heater is demonstrated, opening a path to scaled programming currents. Finally, TiSiN ALD deposition process is proposed as the solution to improve uniformity and scalability of Heater resistance. As Heater is the variable controlling the whole system, this approach guarantees the robustness of $e$ PCM technology for automotive grade-0 applications.

This paper discusses the effect of back-end of line (BEOL) process on cell performance for a Phase-Change Memory embedded in a 28nm FD-SOI platform (ePCM). The impact of BEOL is first shown by describing the microscopic evolution of the active Ge-rich GST alloy during process. Ge clustering has been proven to occur during the fabrication process, impacting the pristine resistance and the after forming cell performance. Two different BEOL processes are then benchmarked in terms of key performance. An optimized process is then identified, and an extensive electrical characterization of array performance and reliability is performed on the full 16MB chip. The optimized BEOL process results in a memory cell fully compatible with the requirements for demanding automotive applications.

TCAD simulations on 28-nm fully depleted silicon on insulator structures are used to analyze the charge collection mechanism leading to parasitic current when an ionizing particle passes through the devices. A description of the components constituting the parasitic current is carried out for several strike locations. The bipolar effect does not arise as the main cause of the parasitic current as usually reported. The impact of the drain-source polarization in the collection mechanism is highlighted. A compact model was made, and a quantitative effect was simulated for the pass-gates in an SRAM cell using a variation of the bitline supply.

The ultra-thin body-bias (UTBB) and fully- depleted silicon on insulator (FDSOI) 28nm technology offers the capability of extreme low power performance, in part because of the use of ultra-thin buried oxide. This unique capability could be jeopardized by the probability of over etching the buried oxide layer during the formation of contacts, with potential generation of electrical short with the substrate. We used SEMulator3D virtual fabrication platform from Coventor to model the contact punch-through mechanism. We then run a design of experiment with the model to quantify the sensitivity of each process variable. Finally we used the virtual fabrication methodology to improve the robustness of the process.

Among the numerous ways to address 3D stacking of integrated circuits, a promising method is Cu/SiO 2 hybrid bonding, which is the simultaneous metallic bonding of the interconnection pads and direct bonding of the dielectric surfaces. Prior to bonding, a chemical-mechanical polishing step is necessary, resulting in copper pads being slightly overpolished compared to the surrounding oxide regions (dishing effect). This effect, if too important, can prevent bonding and thereby lead to electrical connection failure between top and bottom parts. In order to better understand the involved phenomena and to perform virtual prototyping, a 3D finite element model for the thermal annealing of Cu/SiO 2 hybrid bonded pads is presented, taking into account the dishing effect. In this work, the contributions to bonding of thermoelastic deformation and cohesive interactions are investigated, and the impact of pad shape on Cu-Cu interface closure during thermal annealing studied. In addition, a parametric study is conducted, in order to identify the most efficient design and process parameters to improve bonding quality.

An enhanced trench first hard mask (TFHM) backend integration architecture has been developed to facilitate straightforward ultra low-k (ULK) material insertion and to enable rapid yield learning at the 65nm technology node. Parametric, yield, reliability, and RC performance data are presented for the fully-integrated, improved TFHM 300mm ULK backend

Given the much discussed challenges of interconnect scaling at the 65-nm node, the choice of process architecture is a key determinant of performance and extendibility. An alternate trench-first with hardmask integration is described in this work, including subsequent benefits. BEOL design rules are detailed for the 65-nm architecture, supporting both "low-k" and "ultra-low-k" backends, satisfying RC scaling requirements. Electrical parametric performance and yield are presented for a fully-integrated 300mm backend utilizing 65-nm design rules demonstrating the viability of this architecture for the 65-nm node and beyond.

Integration of three level of SiO2 air gap has been successfully achieved in a complete CMOS copper interconnect scheme. SiO2 air gap is demonstrated to be a reliable ultra low k for sub 0.1 mum technologies with a well controlled dielectric constant below 2.

Electromigration and the effects of Cu concentration in intra-metal dielectrics have been examined: these two key reliability issues are fundamental in the development of Cu based interconnects. Several experiments have been performed to highlight the sensitivity of the electromigration performances with respect to the various process variants: the impact of annealing, of dielectric capping SiN deposition process and the role of the environment on the diffusion mechanisms have been studied. Furthermore, the dependence of the line-width on the current and temperature induced transport mechanisms have been analyzed. Once more, process variations have been demonstrated to influence strongly the final behavior of Cu interconnects in dual-damascene architecture. Intra-metal dielectric reliability has also to be considered as a potential reliability issue and bias-temperature stress tests have proven that if the amount of Cu left behind the barrier during the process is not precisely controlled, the role of the barrier as a diffusion inhibitor could be questionable.

Time-Dependent-Dielectric-Breakdown tests have been conducted on differently copper-contaminated SiO/sub 2/ Metal-Oxide-Silicon (MOS) capacitors. It has been demonstrated that TDDB tests are particularly sensitive in addressing the properties of Cu-contaminated dielectric and hence are suitable for the characterization of diffusion barrier layers for Cu based interconnects. The analysis of the lifetime dependence of the interlevel dielectric (ILD) with respect to Cu contamination clearly shows that not only the metal must be well encapsulated by diffusion barrier layers, but that the amount of Cu left behind the barrier by technological process steps should be minimized. Without effective cleaning steps any effort made in providing strong diffusion barrier could vanish.

The impact of IC fabrication process steps on electrical and reliability characteristics of dual damascene copper interconnects has been analyzed. It is demonstrated that thermal treatments could have a negative impact on electrical performances unless a suitable encapsulation step of copper lines is performed. Electromigration performances are also strongly affected by annealing and the role that impurities have in dominating the diffusion paths is evidenced by experiments on differently fabricated copper structures of various widths.

We have studied the effect of texture (X-ray diffraction pole figures) and grain morphology (Focus Ion Beam cross-sections) on the electromigration performances of copper damascene interconnects. Three different metallizations have been characterized: Chemical Vapor Deposition copper deposited on TiN (process A) and electroplated copper deposited either on Ta (process B) or TaN (process C). The reliability performance of these interconnects has been evaluated using both Wafer Level Reliability (WLR) and Package Level Reliability (PLR) tests on 4 and 0.6 νm wide lines using single metal level test structures. On the basis of the activation energy values and failure analysis observations, we concluded that interfacial diffusion plays a key role in the electromigration phenomenon for processes B and C whereas grain boundaries seem to be the active diffusion path for process A. The existence of several failure mechanisms during electromigration tests (interfacial or grain boundary diffusions), the impact of the damascene architecture on microstructure (sidewall textures and non columnar grain shapes) and the copper propensity for twinning seem to mask the impact of texture on the electromigration reliability of copper damascene interconnects.

We have completed a set of experiments on damascene Chemical Vapor Deposition Copper (CVD-Cu) interconnects using Wafer Level and Package Level Reliability (WLR and PLR) tests. Two line widths have been extensively characterized : w=4 and 0.6 μm. For both line widths, the activation energy values extracted using WLR and PLR data are good in agreement demonstrating that the active diffusion paths remain the same over the wide range of used measurement conditions : Ea=0.65eV for w = 4μm, Ea = 0.7-0.8eV for w = 0.6μm. spite of Ea experimental values lower than the reference values of the literature.

The purpose of this paper is to show that in advanced sub-0.5 mum technologies, short-time classical Hot-Carrier (HC) stress tests are suitable for a predictive in-line monitoring. The ability of such tests in detecting maverick lots and the comparison with the performances of an already proposed fast method, lead to consider this approach as very attractive for wafer-level reliability control (WLRC) purposes.

Time-Dependent-Dielectric-Breakdown (TDDB) tests have been conducted on differently copper-contaminated Metal-Oxide-Silicon (MOS) capacitors in which the insulator was the same as the interconnects Inter-Level Dielectric (ILD). TDDB tests are particularly sensitive in addressing the properties of Cu-contaminated dielectric and they are suitable for the characterization of diffusion barrier layers for Cu based intconnects. The lifetime dependence of ILD on Cu contamination clearly shows that the lost of insulating performances can be a new degrading mechanism related to Cu-based interconnects. It is also shown that technological process steps could impact the reliability of Cu interconnects: without effective cleaning steps any effort made in providing strong diffusion barrier could vanish.