We present a self-consistent 2-D quantum-mechanical model for charge distribution in cylindrical gate-all-around devices with computation of the gate tunneling current. The validity of 1-D approximations for the charge and the gate current is discussed, assessing the validity of a previously proposed analytical approximation for the tunneling current in the Fowler-Nordheim regime.

We present a new erase saturation issue compromising the performance of cylindrical charge-trap cells integrated along junction-less NAND strings. The phenomenon comes from the inability to properly induce an inversion layer in the inter-cell regions of the string during read in the cylindrical geometry, pinning the threshold voltage (VT) resulting from cell erase. The dependence of this issue on string parameters is investigated, showing that a reduction in the inter-cell regions may relieve it. However, this originates a trade-off against the constraints raised by the lateral diffusion of electrons in the charge-trap layer during data retention. It is shown that this trade-off can be easily managed by strings with large substrate radius, while its solution is more critical for small radii.

This paper presents a comprehensive numerical modeling for the threshold-voltage transients of nitride-based memory devices during programming, erasing and data retention. The developed numerical tool self-consistently solves the Poisson, continuity and trapping equations in the nitride layer using a drift-diffusion formalism. The continuity equation has been discretized using the Scharfetter-Gummel scheme and a modified Gummel-map has been optimized to ensure fully convergence of the equations. The numerical model is able to describe the memory device operation for different gate bias regimes, therefore addressing both the program/erase and the retention conditions. Finally, numerical results are shown to carefully reproduce experimental data on template devices with different gate stack compositions, validating the physical assumptions and making the model a valuable tool for nitride memories investigation and design. (C) 2010 Elsevier Ltd. All rights reserved.

This paper presents a detailed investigation of charge-trap memory programming by means of 3-D TCAD simulations accounting both for the discrete and localized nature of traps and for the statistical process ruling granular electron injection from the substrate into the storage layer. In addition, for a correct evaluation of the threshold-voltage dynamics, cell electrostatics and drain current are calculated in presence of atomistic doping, largely contributing to percolative substrate conduction. Results show that the low average programming efficiency commonly encountered in nanoscaled charge-trap memory devices mainly results from the low impact of locally stored electrons on cell threshold voltage in presence of fringing fields at the cell edges. Programming variability arising from the discreteness of charge and matter will be addressed in Part II of this paper.

This paper investigates the statistical variability sources affecting the program operation of nanoscale charge-trap memories. Using the 3-D TCAD model presented in Part I of this work, featuring a Monte Carlo simulation approach to deal with discrete traps in the storage layer, atomistic doping in the substrate, and granular electron injection from the substrate to the storage layer, we consider the effect of three main variability sources impacting charge-trap memory programming: 1) the statistical process ruling electron injection and trapping; 2) the fluctuation in the number and position of the trapping sites; and 3) the statistical distribution of the threshold-voltage shift induced by stored electrons in presence of percolative substrate conduction. We show that the first variability source plays the dominant role in determining the statistical dispersion of cell threshold voltage during the program operation.

This paper investigates the impact of lateral charge migration on the retention performance of charge-trap memories whose storage layer is not patterned self-aligned with the channel area of each cell. Experimental results on planar SONOS devices, revealing an important contribution of lateral charge migration at 150 °C, are used to calibrate a new numerical model accounting for both the vertical and the lateral charge loss from the silicon nitride. Modeling results allow a detailed analysis of the retention transients of both planar and 3D SONOS arrays, evaluating, for the latter, the minimum dimensions needed to fulfill the retention requirements at 85 °C.

The aim of this work is to understand charge loss mechanisms in TANOS stack for which charge retention is monitored just after programming in an almost continuous way and voltage is applied during retention experiments in order to obtain zero electric field either on alumina or tunnel oxide. The charge loss mechanisms in TANOS stack can be a quite complicated process: An initial fast DT from interface traps localized at SiN/alumina interface, followed by charge loss through alumina from bulk traps in SiN which influences charge redistribution towards the tunnel oxide, observed only in Si-rich SiN. Programming voltage and stack composition impact trapped charge localization and hence charge redistribution and charge loss, even if the same initial Vfb is considered in charge retention experiments. While the charge loss through tunnel oxide is a DT, the charge loss through alumina depends on temperature and it is the main component of the charge loss in retention experiments for longer time.

We present a detailed semi-analytical investigation of the transient dynamics of gate-all-around (GAA) charge-trap memories. To this aim, the Poisson equation is solved in cylindrical coordinates, and a modification of the well-known Fowler-Nordheim formula is proposed for tunneling through cylindrical dielectric layers. Analytical results are validated by experimental data on devices with different gate stack compositions, considering a quite extended range of gate biases and times. Finally, the model is used for a parametric analysis of the GAA cell, highlighting the effect of device curvature on both program/erase and retention.

We present a comprehensive investigation of the programming dynamics of nanoscale charge-trap memories, based on 3D Monte Carlo simulations accounting for: 1) true 3D electro-statics during programming and read; 2) atomistic substrate doping; 3) discrete traps, fluctuating in number and position, with localized electron storage; 4) discrete electron injection into traps. The model allows to clarify several key issues affecting the program operation of charge-trap memories, most notably the reduced slope of the ISPP transients exhibited by scaled cells, the programming variability, and the width of the final programmed threshold-voltage distribution. Results are of utmost importance for the assessment of the true programming performance of nanoscale charge-trap memory technologies.

This paper presents a comprehensive investigation of statistical effects in deeply scaled nitride memory cells, considering both atomistic substrate doping and the discrete and localized nature of stored charge in the nitride layer. By means of 3-D TCAD simulations, the statistical dispersion of the threshold voltage shift induced by a single localized electron in the nitride is evaluated in presence of non-uniform substrate conduction. The role of 3-D electrostatics and atomistic doping on the results is highlighted, showing the latter as the major spread source. The threshold voltage shift induced by more than one electron in the nitride is then analyzed, showing that for increasing numbers of stored electrons a correlation among single-electron shifts clearly appears. The scaling trend and the practical impact of these statistical effects on cell operation are discussed in Part II of this paper.

This paper presents a detailed investigation of the ISPP dynamics of charge-trap memory capacitors, considering not only the flat-band voltage but also the bottom oxide electric field and tunneling current evolution during programming. Differently from the floating-gate case, results on nitride-based memories show that the flat-band increase per step does not equal the step amplitude of the gate staircase, decreasing, moreover, as programming proceeds. As a consequence, the electric field and tunneling current through the bottom oxide are shown to largely increase. Using results at different temperatures and on samples with different stack compositions, this dynamics is explained in terms of a drop of the programming efficiency as more and more charge is stored in the nitride layer, due to the reduction of the number of free traps available for capturing the injected electrons.

In this work we present a detailed investigation of TANOS memory reliability, focusing on issues raised by Al2O3 trapping/detrapping and leakage. These effects are investigated as a function of alumina thickness, electric field and temperature, comparing experimental and modeling results for trap parameters extraction. For TANOS devices, Al2O3 charge storage modifies program and erase saturation level particularly when higher Al2O3 thikness are considered. Threshold instability in early steps for endurance and retarded behavior for retention can be also ascribed to the Al2O3 trapping. Moreover, Al2O3 layer has been shown to provide the main leakage path for bottom oxides thickness in the 4.5 nm or above range.

This paper presents a scaling analysis of the statistical distribution of the threshold voltage shift (ΔVT) obtained by electron storage in nitride memories, considering both its average and standard deviation. For fixed density of trapped charge, the average ΔVT decreases as a consequence of fringing fields, not predictable by any 1-D simulation approach. Moreover, the distribution statistical dispersion increases with technology scaling due to a more sensitive percolative substrate conduction in the presence of atomistic doping and 3-D electrostatics. The impact of these effects on device performance is then highlighted, showing that the accuracy of the staircase programming algorithm can be reduced further from the limitation given by the electron injection statistics during programming. The impact of electron storage in the nitride on random telegraph noise instabilities is also investigated, showing that, despite single cell behavior may be modified, negligible effects result at the statistical level.

This paper presents a physics-based model that is able to describe the TANOS memory programming transients in the Fowler-Nordheim uniform tunneling regime across the bottom-oxide layer.The model carefully takes into consideration the trapping/detrapping processes in the nitride, the limited number of traps available for charge storage, and their spatial and energetic distribution.Results are in good agreement with experimental data on TANOS devices with different gate-stack compositions, considering a quite extended range of gate biases and times.The reduced gate-bias sensitivity of the programming transients with respect to the floating-gate cell is explained in terms of a finite number of nitride traps and a thinner extension of the nitride trapping region as the gate bias is increased.The model represents a valid contribution for the investigation of the achievable performances of the TANOS technology.

We present a new physics-based model able to reproduce the program/erase transients in TANOS memories, accurately describing the charge trapping/detrapping dynamics in the nitride layer. Modeling results are extensively validated against a large number of experimental data taken on samples with different gate stack compositions, considering a quite extended range of program/erase voltages and times. The good agreement between experimental and simulated results makes the developed model a useful tool for the assessment of the performance achievable by the TANOS technology.